Semiconductor Memory Plane Synchronous Control via Shared Address Bus
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Solution Overview
Problem
The increasing number of planes in semiconductor memory devices leads to an expansion in circuit and wiring areas due to the need for more signal lines and block address registers for synchronous operations, which complicates the design and increases complexity.
Innovation Solution
The implementation of a configuration where multiple planes are operated in synchronization using a reduced number of signal lines and block address registers, with block addresses being transferred in series and stored in registers before selection, allowing for efficient synchronous operations without a significant increase in circuit and wiring areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple planes are operated in synchronization, then productivity is improved, but device complexity increases due to more signal lines and block address registers
Solution Approach 1:
The patent merges the block address transfer and selection functions into a single shared bus structure. Multiple planes share common block address buses (BA0-BA3) and control signals, eliminating the need for separate dedicated signal lines for each plane. This combining approach allows synchronous operation of multiple planes while preventing the linear increase in signal lines that would normally occur.
Solution Approach 2:
The control circuit is designed with universal, multi-functional components that can serve multiple planes simultaneously. The same block address registers and decoders are reused across different planes through time-multiplexed addressing, allowing a single set of control logic to manage synchronous operations across multiple planes without requiring plane-specific duplicate circuits.
2Quantity of substance
If the number of planes is increased, then storage capacity is improved, but circuit area increases due to additional signal lines and registers
Solution Approach 1:
The patent combines multiple plane control functions into shared circuit resources. By merging block address bus connections and using common control signal lines for multiple planes, the circuit area required for wiring and control logic is significantly reduced compared to having separate dedicated paths for each plane, thus allowing storage capacity to scale without proportional increases in circuit area.
Solution Approach 2:
The patent introduces a plane selection dimension through control signals that enable multiple planes to share the same physical wiring infrastructure. By adding logical plane identification to the addressing scheme rather than creating separate physical paths, the system achieves increased storage capacity while maintaining compact circuit layout.
Data Source
AI summary
A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.