Nonvolatile Memory Plane Timing Control for Power Noise Mitigation
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Solution Overview
Problem
Flash memory devices face significant delays during erase operations due to their physical characteristics, which hinder efficient data overwrite processes, impacting performance in storage devices.
Innovation Solution
A nonvolatile memory device with a control logic circuit that manages the execution of sub-operations on multiple planes, delaying operations to avoid overlap and adjust timing based on reference times to mitigate power noise effects, allowing for more efficient data management and overwrite operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory performs erase operations on a per-block basis, then data can be overwritten, but significant time is required for the erase operation
Solution Approach 1:
The memory device is divided into multiple planes, with each plane independently capable of performing read/program operations. This segmentation allows parallel operations across planes, reducing the effective time for data management tasks while maintaining overwrite capability through coordinated plane operations.
Solution Approach 2:
The control logic circuit determines potential noise sections and victim sections in advance, and pre-calculates appropriate delay times for victim sections. This preliminary action prevents power noise interference before it occurs, eliminating the need for lengthy erase operations to correct noise-induced errors.
2Productivity
If multiple planes operate simultaneously, then operational efficiency increases, but power noise from noise sections can interfere with victim sections
Solution Approach 1:
The control logic circuit acts as an intermediary that monitors operations across all planes, identifies potential noise sections and victim sections, and introduces calculated delay times for victim sections. This intermediary control mechanism enables simultaneous multi-plane operations while preventing power noise interference through timing coordination.
Solution Approach 2:
The system dynamically adjusts operation timing by varying delay times for victim sections based on real-time identification of noise sections. This dynamic timing adjustment allows flexible coordination of multi-plane operations, maintaining high productivity while adaptively preventing power noise interference.
3Adaptability or versatility
If erase operations are performed frequently to enable overwriting, then data update capability improves, but device wear and operation time increase
Solution Approach 1:
The system converts the harmful effect of power noise into a beneficial timing adjustment mechanism. By identifying noise sections and applying calculated delays to victim sections, the system prevents noise-induced errors that would otherwise require corrective erase operations, thereby reducing wear and extending device lifespan while maintaining data update capability.
Data Source
AI summary
A nonvolatile memory device includes control logic and a memory cell array. The memory cell array includes a first plane and a second plane. The control logic is configured to perform a first sub-operation on the first plane, to perform a second sub-operation on the second plane, to delay the second sub-operation as much as a reference time so that a partial section of the first sub-operation does not overlap the second sub-operation, and to variably control the reference time.