Nonvolatile Memory Plane Voltage Control for Erase Efficiency

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Solution Overview

Problem

Current memory devices face challenges in enhancing performance and efficiency during erase operations, particularly in distinguishing and managing erase completion and non-completion planes effectively.

Innovation Solution

A nonvolatile memory device is designed with a voltage generator that selectively applies different ground selection voltages to planes based on the result of an erase verification operation, ensuring appropriate voltage application to erase completion and non-completion planes to optimize erase operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single ground selection voltage is applied to all planes, then the device structure is simple and easy to control, but the erase operation efficiency is reduced because all planes must be processed uniformly regardless of their erase completion status

Engineering Contradiction:

Improveerase operation efficiencyVSAvoidvoltage control complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The memory device divides the planes into multiple groups (first group and second group) and applies different ground selection voltages to each group based on erase verification results. This segmentation allows independent voltage control for erased and non-erased planes, improving erase efficiency without requiring complex per-plane control.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different ground selection voltages (first ground selection voltage and second ground selection voltage) are applied to different plane groups according to their specific erase status. Erased planes receive one voltage while non-erased planes receive another, allowing optimized erase operations for each group's specific condition.

Inventive Principle:

Principle #3Local quality

2Reliability

If erase verification is performed on all planes, then the erase completion status can be accurately determined, but the operation time increases

Engineering Contradiction:

Improveerase completion accuracyVSAvoiderase operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The device performs erase verification on a first group of planes before completing the erase operation on all planes. Based on the verification results, planes are divided into different groups that receive different ground selection voltages during the erase operation, allowing early identification and separate handling of erased planes.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The erase verification is performed partially on only the first group of planes rather than all planes. This partial verification is sufficient to determine erase completion status for those planes, allowing the system to optimize voltage application without requiring complete verification of all planes.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS9672932B2Nonvolatile memory device and memory system including the same

Publication Date: 2017.06.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory device includes a memory cell array and a voltage generator. The memory cell array includes a plurality of planes, and each plane receives one of a first ground selection voltage and a second ground selection voltage. The voltage generator is configured to provide selectively one of the first ground selection voltage and the second ground selection voltage independently to each of the planes based on a result of an erase verification operation on each of the plurality of planes.