3D Memory Plane Layout for Lower Wiring Resistance
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Solution Overview
Problem
As the level of integration in semiconductor memory devices increases, the number of conductive layers and transistors grows, leading to challenges in efficiently connecting and reducing wiring resistance, which affects the performance and integration density of these devices.
Innovation Solution
The semiconductor memory device is configured with a specific arrangement of conductive layers, transistors, and wiring layers, where the row control circuit region overlaps parts of memory regions and hookup regions, allowing for reduced wiring density and length, thereby minimizing wiring resistance and optimizing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of conductive layers and transistors is increased to improve integration density, then productivity and storage capacity are improved, but wiring resistance increases and manufacturing complexity worsens
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by stacking conductive layers vertically. Multiple bit lines and word lines are arranged in different vertical layers, allowing signals to be routed through the third dimension (stacking direction). This reduces wiring resistance by providing shorter, more direct vertical pathways compared to long lateral connections in conventional planar structures.
Solution Approach 2:
The patent implements nested wiring structures where conductive layers are stacked within each other in a vertical configuration. Each conductive layer is positioned at a different height, creating a nested arrangement that allows multiple signal paths to coexist in a compact volume. This nesting approach enables efficient interconnection of transistors while minimizing wiring length and resistance.
2Productivity
If more conductive layers are stacked to increase integration density, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent segments the wiring structure into multiple independent conductive layers, each serving specific functions (bit lines, word lines, select lines). This segmentation allows each layer to be optimized independently for its specific signal type, simplifying the overall design despite the increased number of layers. Each conductive layer can be formed using standardized processes, reducing manufacturing complexity.
Solution Approach 2:
The stacked conductive layers serve multiple functions simultaneously - acting as bit lines, word lines, and select lines for different memory strings. This multi-functionality reduces the total number of separate wiring structures needed, as the same vertical stacking approach handles various signal routing requirements, thereby reducing overall device complexity.
Data Source
AI summary
A memory plane region includes a first structure and a second structure having conductive layers, and includes a first memory region to a third memory region, a first region between the first memory region and the second memory region, and a second region between the second memory region and the third memory region. The first structure comprises first via contact electrodes in the first region. The second structure comprises second via contact electrodes in the second region. The first via contact electrodes are electrically connected to transistors provided at positions where the first structure and the first region overlap, and where the second structure and the first region overlap. The second via contact electrodes are electrically connected to transistors provided at positions where the first structure and the second region overlap, and where the second structure and the second region overlap.