Memory Controller PLL Trimming for High Data Rate Stability
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Solution Overview
Problem
Existing memory devices face challenges in achieving high data rates while maintaining low phase noise, as current phase-locked loop (PLL) management introduces side effects that affect performance.
Innovation Solution
A method for on-system PLL management in memory devices using a trimming control circuit to adjust voltage parameters of a voltage-controlled oscillator (VCO) within the PLL, optimizing the PLL for high data rates without introducing unwanted side effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a phase-locked loop (PLL) is used in the PHY circuit to achieve high data rate, then data transmission speed is improved, but phase noise increases affecting performance
Solution Approach 1:
The patent implements on-system PLL management by dynamically adjusting PLL parameters (such as divider ratios, reference frequencies, and trim values) based on detected signal conditions. This allows the system to optimize the balance between data rate and phase noise by changing operational parameters rather than being fixed at a single operating point.
Solution Approach 2:
The system employs feedback mechanisms where the PLL performance is continuously monitored and adjusted. The controller reads status registers and adjusts PLL control registers based on detected phase noise levels and locking conditions, creating a closed-loop system that adapts to maintain optimal performance.
2Reliability
If PLL parameters are adjusted to reduce phase noise, then phase noise is reduced, but data rate capability is compromised
Solution Approach 1:
The patent makes the PLL system dynamic by enabling real-time parameter adjustment during operation. Instead of fixed parameters, the system can adaptively change divider ratios, reference frequencies, and other PLL parameters based on current transmission conditions, allowing optimization for both speed and phase noise as needed.
Solution Approach 2:
The system changes operational parameters dynamically to resolve the contradiction. By adjusting parameters such as the reference clock frequency, divider ratios, and trim values based on detected performance metrics, the system can shift between optimization modes for data rate versus phase noise reduction.
3Device complexity
If traditional PLL management methods are used, then implementation is simple, but side effects are introduced affecting overall performance
Solution Approach 1:
The patent implements self-service PLL management where the system automatically detects its own performance issues and adjusts parameters without external intervention. The controller monitors PLL status registers and autonomously modifies control parameters, eliminating the need for complex external calibration equipment or manual tuning procedures.
Solution Approach 2:
The system uses feedback from status registers to automatically adjust PLL parameters. By reading feedback information about locking status, phase noise levels, and operational conditions, the controller can make informed adjustments to control registers, achieving sophisticated management without increasing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures high stability and low phase noise, enabling short settling times and accurate frequency control, thus enhancing overall memory device performance without introducing side effects.
Implementation Method 1
a voltage controlled oscillator (VCO) in the PLL is implemented with a voltage controlled crystal oscillator (VCXO)
Implementation Method 2
a phase-locked loop (PLL) having low phase noise capability is typically needed in the PHY circuit
Data Source
AI summary
A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.