Memory PLRESET Handling for Bad Block Risk Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory systems inadequately handle power-loss reset events, leading to good blocks being mistakenly marked as bad and memory dies being retired prematurely, especially under high-frequency input noise and reduced supply voltage conditions, which impacts operational performance and reliability.
Innovation Solution
Implement a technique in memory systems to mitigate the risk of marking good blocks as bad and premature die retirement by temporarily adjusting PLRESET thresholds, performing additional tests on blocks, and using error-correction techniques to recover data, thereby maintaining system performance and reducing unnecessary block marking and die retirement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLRESET threshold is lowered to detect power-loss events, then reliability of power-loss detection is improved, but good blocks are mistakenly marked as bad
Solution Approach 1:
The patent segments the response to PLRESET events by creating different handling paths: immediate bad block marking for PLRESET LOW events, and deferred testing for normal PLRESET events. This segmentation allows the system to maintain high detection sensitivity while reducing false positives through subsequent verification testing.
Solution Approach 2:
The patent performs preliminary actions by immediately marking blocks as bad when PLRESET LOW events occur, then subsequently testing these blocks to potentially revert the marking. This preliminary action ensures that potential failures are caught early while providing a correction mechanism through follow-up testing.
2Reliability
If PLRESET threshold is lowered to detect power-loss events, then detection sensitivity is improved, but memory die is retired prematurely
Solution Approach 1:
The patent segments die retirement logic by distinguishing between PLRESET LOW events (which trigger immediate retirement) and normal PLRESET events (which undergo block-level testing before die retirement). This segmentation prevents premature die retirement by providing an intermediate testing stage for normal events.
Solution Approach 2:
The patent implements feedback mechanisms where blocks marked as bad due to PLRESET events are subsequently tested to verify their status. This feedback loop provides correction opportunities, preventing false positives from triggering unnecessary die retirement and extending memory die operational lifespan.
3Measurement precision
If additional testing is performed on blocks to verify status, then false positive reduction is improved, but system complexity increases
Solution Approach 1:
The patent applies local quality by performing additional testing only on specific blocks that were marked as bad due to PLRESET events, rather than implementing universal complex testing for all blocks. This targeted approach improves verification accuracy while minimizing added system complexity.
4Reliability
If data is moved during PLRESET event handling, then data integrity is improved, but operational performance decreases
Solution Approach 1:
The patent implements periodic action by moving data during idle periods or scheduled maintenance windows rather than during active operations. This approach ensures data integrity during power-loss events while minimizing the impact on operational performance by performing data movements when system load is lower.
Data Source
AI summary
Various example embodiments provide for handling a power-loss reset (PLRESET) event in a memory system, such as a memory sub-system, with a technique that mitigates the risk of a good block being marked as bad, a memory die being retired prematurely, or both.