3D Memory Plug Spacer Structure for Misalignment Isolation
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Solution Overview
Problem
In three-dimensional non-volatile memory semiconductor storage devices, misalignment between pillars and plugs can lead to physical or electrical contact, causing short circuits and reducing alignment accuracy.
Innovation Solution
A semiconductor storage device design featuring a plug with a lower dielectric constant spacer insulating layer surrounding the plug, which has a larger diameter than the pillar, preventing contact with adjacent pillars and reducing parasitic capacitance, while maintaining alignment accuracy through specific layer thickness conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pillar and plug are aligned with high precision, then alignment accuracy is improved, but manufacturing complexity increases due to the need for precise positioning structures
Solution Approach 1:
The patent introduces a spacer insulating layer as an intermediary element between the plug and the select gate line. This spacer layer acts as a positioning mediator that automatically maintains the required spacing and alignment through its physical presence and dielectric properties, eliminating the need for complex active positioning mechanisms while ensuring manufacturing precision.
Solution Approach 2:
The spacer insulating layer is formed in advance during the manufacturing process to pre-establish the correct spatial relationship between the plug and select gate line. This beforehand cushioning approach prevents alignment issues before they occur during device operation, rather than requiring complex real-time positioning structures.
2Reliability
If the plug diameter is increased to prevent misalignment contact, then reliability is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by creating a spacer insulating layer with specific dielectric properties only in the critical region between the plug and select gate line. This localized approach provides enhanced insulation and short circuit prevention exactly where needed, while maintaining smaller plug dimensions in non-critical areas to minimize parasitic capacitance.
Solution Approach 2:
The spacer insulating layer serves as an intermediary dielectric barrier that prevents direct contact between the plug and select gate line. This mediator layer provides reliable electrical isolation without requiring an increased plug diameter, thereby preventing short circuits while maintaining low parasitic capacitance.
3Reliability
If a spacer insulating layer is added around the plug, then reliability is improved by preventing contact, but device complexity increases
Solution Approach 1:
The patent merges the spacer insulating layer formation with existing manufacturing processes by integrating it into the insulating layer deposition sequence. The spacer layer is formed as part of the overall insulating layer structure, combining multiple functions (isolation, spacing, and structural support) into a unified layer system rather than adding separate complex components.
Solution Approach 2:
The spacer insulating layer performs multiple functions simultaneously: it provides electrical isolation between the plug and select gate line, maintains proper spacing through its physical thickness, and serves as part of the overall insulating layer structure. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents short circuits between plugs and select gate lines, enhances alignment accuracy, and reduces parasitic capacitance, ensuring reliable operation and improved withstand voltage.
Implementation Method 1
a spacer insulating layer which surrounds the plug inside the upper insulating layer and has a lower dielectric constant than a dielectric constant of the upper insulating layer
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes: a stacked body in which a plurality of conductive layers are separated from each other and are stacked; a pillar which extends in a stacking direction and includes memory cells to be formed at intersections with at least some of the plurality of conductive layers; an upper insulating layer arranged on the stacked body; a plug which extends in the stacking direction inside the upper insulating layer and is connected to the upper end portion of the pillar; and a spacer insulating layer which surrounds the plug and has a lower dielectric constant than a dielectric constant of the upper insulating layer.