Memory Module Power Control via PMIC Segmentation
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Solution Overview
Problem
Traditional information handling systems lack effective control over power delivery to individual memory modules, leading to prolonged power consumption and potential electrical damage when a memory chip fails, which can cause power faults and affect system uptime.
Innovation Solution
An information handling system with a host processor executing a basic input/output system to monitor memory modules for faults and control circuitry to de-assert the power control signal if all associated memory modules experience faults, effectively de-energizing them to prevent further damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory chip fails and is mapped out from total system memory, then the failed memory chip is isolated from system operations, but the power consumed by the entire memory module continues indefinitely until manual removal or replacement
Solution Approach 1:
The patent segments the memory module into independently controllable power domains by introducing a power management integrated circuit (PMIC) that can selectively de-energize individual memory chips or groups of chips within a memory module. This allows the system to isolate only the failed memory chip while keeping other functional chips powered, thereby resolving the contradiction between maintaining system reliability and reducing unnecessary power consumption.
Solution Approach 2:
The patent implements dynamic power management by enabling the system to adaptively control power delivery to memory modules based on their operational status. When a memory chip fails, the system dynamically adjusts the power state by de-asserting power control signals to the affected chips while maintaining power to functional chips, thus optimizing the balance between reliability and energy efficiency.
2Reliability
If the system continues to poll PMIC registers and explicitly disable bad memory chips, then the failed chips are identified and isolated, but cold and warm boot times increase significantly
Solution Approach 1:
The patent applies preliminary action by performing memory chip validation and power state configuration during the manufacturing or initialization phase, rather than during each boot sequence. The system pre-configures power control signals and PMIC settings based on known good or bad chips, so that during normal operation including boot, the system can quickly activate or deactivate specific chips without extensive polling or registration checks, thereby reducing boot time while maintaining reliable fault detection.
3Adaptability or versatility
If a bad memory chip is left powered indefinitely, then the system maintains operational flexibility, but electrical damage can spread to other memory modules through power faults
Solution Approach 1:
The patent extracts the harmful electrical effects from the system by physically isolating the failed memory chip through de-energization. The PMIC acts as an intermediary that can disconnect power to the failed chip while maintaining power to the rest of the memory module, thus removing the source of electrical damage propagation while preserving system flexibility through selective power control.
Solution Approach 2:
The patent introduces the power management integrated circuit (PMIC) as an intermediary between the power source and memory chips. The PMIC can selectively assert or de-assert power control signals to individual chips or groups of chips, enabling the system to isolate failed chips and prevent electrical damage propagation while maintaining operational flexibility through fine-grained power control.
Data Source
AI summary
An information handling system may include a memory comprising a plurality of memory modules, each memory module comprising a plurality of memory chips, a host system comprising a host system processor configured to, during a boot of the information handling system, execute a basic input/output system of the information handling system configured to monitor for one or more faults of one or more memory modules of the plurality of memory modules, and control circuitry. The control circuitry may be configured to, in response to the one or more faults, determine if, all of one or more memory modules associated with a power control signal of such one or more memory modules have experienced faults, and if all of the one or more memory modules associated with the power control signal have experienced faults, de-assert the power control signal such that the one or more memory modules are de-energized.