Memory Device With Polysilicon Cell Region
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Solution Overview
Problem
The challenge lies in increasing the degree of integration of semiconductor devices in electronic products while maintaining high data processing capacity, which requires advanced memory device structures that enhance semiconductor device performance and integration.
Innovation Solution
A memory device structure is developed with a COP or POC configuration, where a polysilicon substrate with lateral grains is used for the cell region, formed by crystallizing an amorphous silicon layer using a sequential lateral solidification process, and a single crystalline silicon substrate for the peripheral circuit region, with word-line cuts and epitaxial layers to improve device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a polysilicon substrate with lateral grains is used for the cell region, then the degree of integration and device capacity are improved, but the crystallinity and device performance may be degraded
Solution Approach 1:
The patent applies different substrate types to different functional regions: a single crystalline silicon substrate for the peripheral circuit region requiring high performance, and a polysilicon substrate with lateral grains for the cell region requiring high integration density. This local differentiation resolves the contradiction by optimizing each region for its specific functional requirements.
Solution Approach 2:
The memory device is segmented into two distinct substrate regions with different material properties. The peripheral circuit region and cell region are physically separated and independently optimized, allowing the polysilicon substrate to provide high integration for memory cells while the single crystalline substrate ensures high performance for peripheral circuits.
2Quantity of substance
If the degree of integration is increased to process high capacity data, then data processing capacity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from a single-plane device structure to a stacked three-dimensional architecture where the cell region is positioned above the peripheral circuit region. This vertical stacking enables higher integration density and data processing capacity while maintaining manageable device complexity through modular regional design.
3Reliability
If a single crystalline silicon substrate is used for the peripheral circuit region, then device performance and reliability are improved, but manufacturing complexity increases compared to uniform polysilicon substrates
Solution Approach 1:
The patent applies different substrate types to different functional regions: a single crystalline silicon substrate for the peripheral circuit region requiring high performance, and a polysilicon substrate with lateral grains for the cell region requiring high integration density. This local differentiation resolves the contradiction by optimizing each region for its specific functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the crystallinity and performance of the memory device, increasing integration density and reducing defects, thereby improving overall device efficiency and capacity.
Implementation Method 1
formed by crystallizing an amorphous silicon layer using a sequential lateral solidification process
Implementation Method 2
an epitaxial layer between the second region and the channel area, the epitaxial layer electrically connecting the second region to the channel area
Data Source
AI summary
A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.