Address Translation for Memory Pooling Fragmentation
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Solution Overview
Problem
Memory sub-systems face challenges with fragmentation and inefficient memory allocation due to the indirect mitigation of memory device fragmentation by existing memory pooling techniques, such as the CXL protocol, which can lead to underutilization of memory resources.
Innovation Solution
Implementing an address translation mechanism in the memory sub-system that maps logical devices to configurable logical units, where the memory sub-system controller determines the minimum allocation unit size (MAU) for logical devices and allocates logical units accordingly, reducing fragmentation without significant performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory pooling techniques (e.g., CXL protocol) are used to allocate memory to multiple logical devices, then memory allocation flexibility is improved, but memory device fragmentation is not effectively mitigated leading to resource underutilization
Solution Approach 1:
The patent divides the memory device into multiple logical units, each of which can be independently allocated to different logical devices. This segmentation enables fine-grained memory allocation where each logical unit represents a discrete allocatable entity, allowing the system to allocate memory in smaller, more flexible units rather than large blocks, thereby reducing fragmentation and improving overall resource utilization while maintaining allocation flexibility.
2Productivity
If memory is allocated in large blocks to logical devices, then allocation speed is improved, but memory fragmentation increases leading to inefficient resource utilization
Solution Approach 1:
The memory device is segmented into multiple logical units that can be independently managed and allocated. This allows the system to allocate memory in smaller, more granular units rather than large blocks, reducing fragmentation while maintaining efficient allocation through the structured organization of logical units that can be quickly assigned to logical devices.
Solution Approach 2:
The system dynamically adjusts memory allocation by allocating individual logical units to logical devices based on actual demand. The memory pool manager can dynamically assign or deallocate logical units without fixed block sizes, allowing flexible adaptation to changing memory requirements while minimizing fragmentation and maintaining allocation efficiency.
3Quantity of substance
If memory pooling allows multiple logical devices to access the same memory device, then memory utilization is improved, but address mapping complexity increases
Solution Approach 1:
The patent introduces a memory pool manager as an intermediary layer between logical devices and the physical memory device. This manager maintains mapping information that associates logical device identifiers with specific logical units, simplifying the address translation process. The structured mapping approach reduces complexity by providing a systematic method for tracking and managing memory allocations across multiple logical devices.
Solution Approach 2:
By dividing memory into discrete logical units and maintaining organized mapping information for each unit, the system reduces address mapping complexity. Each logical unit can be independently tracked and mapped to logical devices, creating a manageable structure that scales better than monolithic address mapping approaches.
4Adaptability or versatility
If existing memory pooling protocols are used, then interoperability is improved, but fragmentation mitigation is indirect and insufficient
Solution Approach 1:
The patent implements direct fragmentation mitigation by segmenting the memory device into logical units that can be precisely allocated and tracked. This granular segmentation enables the system to allocate memory in smaller units, reducing the formation of fragmentation gaps and improving overall memory utilization effectiveness compared to indirect mitigation approaches in existing protocols.
Data Source
AI summary
A system including a memory device and an operatively coupled processing device to perform operations determining a size of a minimum allocation unit (MAU) for a plurality of logical devices, dividing the memory device into logical units with a size equal to the MAU, identifying, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device, identifying, using a logical unit identifier (LUI) data structure, a first set of LUI that are available, wherein the first set of LUI identify a first set of logical units, allocating the first set of logical units to the first logical device, and updating an LDI-to-LUI mapping data structure to reflect that the first set of logical units are allocated to the first logical device.