Memory Pool Allocation for Multi-Core Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-core systems, existing memory management techniques face challenges in efficiently allocating shared memory resources among processors, often resulting in performance penalties and complexity due to the need for bus fabrics and caching, which are costly and difficult to manage.
Innovation Solution
A chip selection circuit is used to dynamically allocate memory blocks to processing cores based on program memory requirements, enabling access through data or memory check ports, and allowing for priority-based access, thereby reducing the need for extensive bus fabrics and caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If uniform memory access is used to implement shared memory, then programming simplicity is improved, but memory access performance deteriorates due to uniform access requirements
Solution Approach 1:
The memory pool is divided into multiple memory blocks, each with dedicated data ports and memory check ports. This segmentation allows different cores to access different memory blocks through dedicated paths, improving access performance while maintaining the shared memory model for programming simplicity.
Solution Approach 2:
Different memory blocks have different access characteristics - some are optimized for data access while others are optimized for memory check access. This local quality differentiation allows each core to access memory through the most appropriate port type, improving overall system performance.
2Speed
If non-uniform memory access is used to improve memory access speed, then memory access performance is improved, but system complexity increases
Solution Approach 1:
The memory system is segmented into blocks with dedicated data ports and memory check ports. Each port type handles specific access patterns, creating non-uniform access paths without requiring complex routing logic or bus fabrics.
Solution Approach 2:
Instead of having memory adapt to core access patterns through complex controllers, the invention inverts the approach by having memory blocks provide dedicated ports for different access types. This simplifies the control logic while achieving non-uniform access optimization.
3Adaptability or versatility
If cache memory architecture is implemented for each core, then memory access flexibility is improved, but device area and cost increase
Solution Approach 1:
The invention merges the functionality of multiple cache memory blocks into a single shared pool. By providing dedicated data ports and memory check ports to each memory block, the system achieves cache-like flexibility without replicating entire cache structures for each core, thereby reducing device area.
Solution Approach 2:
The shared memory pool serves multiple functions - it can be accessed by multiple cores simultaneously through different port types, replacing the need for separate cache memories for each core. This multi-functionality reduces overall device area while maintaining access flexibility.
4Adaptability or versatility
If extensive bus fabrics are used to connect cores to memory, then memory access capability is improved, but device complexity and area increase
Solution Approach 1:
The memory pool is segmented into blocks with dedicated data ports and memory check ports. This segmentation eliminates the need for complex bus fabrics by providing direct, dedicated access paths from cores to memory blocks, thereby reducing device complexity while improving access capability.
5Adaptability or versatility
If extensive caching is implemented to manage shared memory, then memory management capability is improved, but device area and complexity increase
Solution Approach 1:
The invention merges cache functionality into the shared memory pool structure itself. By providing dedicated data ports and memory check ports to memory blocks, the system achieves efficient memory management without requiring separate cache structures, thereby reducing device area and complexity.
Data Source
AI summary
An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.