Memory Pool Allocation for Embedded SRAM Leakage Reduction
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Solution Overview
Problem
Embedded systems in user equipment, such as those supporting LTE and WiMAX, face high leakage power consumption due to the large size of on-chip SRAM required for data packet storage, despite dynamic power efficiency, as the leakage power increases with system integration and is not effectively managed by existing memory management solutions.
Innovation Solution
A memory management system that employs memory-pool based dynamic allocation, aware of physical memory block configurations, to identify and maximize unused memory blocks by dynamically switching their power states based on run-time utilization, using active, retention, and power-off modes to minimize leakage power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If on-chip SRAM is used for data packet storage to meet throughput requirements, then dynamic power consumption is reduced, but leakage power consumption increases with system integration
Solution Approach 1:
The patent divides the SRAM memory into multiple independently controllable blocks or segments. Each block can be selectively activated or deactivated based on actual usage requirements. This segmentation allows the system to maintain low leakage power by keeping unused blocks in a low-power state while preserving the ability to provide high throughput when needed by activating only the necessary blocks.
Solution Approach 2:
The patent implements dynamic power management by changing the operational state of memory blocks from static to dynamic. Memory blocks can transition between different power states (active, retention, or power-down) based on runtime characteristics of data traffic. This dynamic approach allows the system to adapt power consumption to actual workload requirements, resolving the contradiction between maintaining throughput capability and reducing leakage power.
2Reliability
If memory blocks are kept active to ensure availability for packet storage, then system performance is maintained, but leakage power consumption increases
Solution Approach 1:
The patent implements periodic monitoring and evaluation of memory usage patterns. The system periodically assesses which memory blocks are actually in use based on runtime traffic characteristics and adjusts power states accordingly. This periodic action ensures that memory blocks remain active only when needed for packet storage, while being deactivated during periods of low demand, thus maintaining system performance while reducing leakage power.
Solution Approach 2:
The patent employs feedback mechanisms that continuously monitor memory access patterns and traffic characteristics. Based on this feedback, the system dynamically adjusts the power state of memory blocks. When feedback indicates low usage, blocks are deactivated to reduce leakage power; when feedback shows high usage or critical packet storage needs, blocks are activated to maintain system performance and reliability.
3Reliability
If the packet buffer size is increased to handle worst-case operating conditions, then QoS requirements are met, but leakage power consumption increases
Solution Approach 1:
The patent segments the packet buffer into multiple smaller blocks rather than using a single large buffer. This segmentation allows the system to allocate and power up only the necessary portion of the buffer for current traffic conditions, while keeping other portions in a low-power state. The segmented approach maintains the ability to handle worst-case scenarios when needed while significantly reducing leakage power during normal operation.
Solution Approach 2:
The patent dynamically changes the effective buffer size parameter based on runtime traffic characteristics. Instead of maintaining a fixed large buffer size, the system adjusts the active buffer capacity according to actual usage patterns. When traffic conditions are normal, the effective buffer size is reduced to minimize leakage power; when worst-case conditions are detected, the buffer capacity is expanded to meet QoS requirements.
Data Source
AI summary
Embodiments of the invention provide a memory allocation module that adopts memory-pool based allocation and is aware of the physical configuration of the memory blocks in order to manage the memory allocation intelligently while exploiting statistical characters of packet traffic. The memory-pool based allocation makes it easy to find empty memory blocks. Packet traffic characteristics are used to maximize the number of empty memory blocks.