Port-Based Memory Pool Routing for Scalable Low-Latency Access
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Solution Overview
Problem
Existing computing systems face challenges in efficiently routing communications between memory nodes of a memory pool due to varying latencies, limiting the ability to increase coverage span and scale, especially when stringent latency requirements are imposed by certain applications or workloads.
Innovation Solution
A system and method for port-based routing (PBR) in a cache coherent protocol-based interconnect, utilizing a multi-dimension array of memory nodes connected via a switching fabric, where each node is encoded with a first and second identifier to optimize access based on dimension and location, allowing scalable and efficient memory access with varying latency characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory nodes are connected through multiple hops in a memory pool, then the coverage span increases, but the latency increases
Solution Approach 1:
The patent introduces a hierarchical dimension to the memory pool architecture, organizing memory nodes into multiple layers (first memory layer, second memory layer, etc.). Each layer operates with its own identifier system, allowing the system to scale coverage span by adding layers while maintaining low latency within each layer through direct connections. This dimensional organization resolves the contradiction by separating the coverage function (achieved through multiple layers) from the latency function (maintained within single layers).
Solution Approach 2:
The memory pool is segmented into discrete memory layers, with each layer containing specific memory nodes identified by unique identifiers. This segmentation allows independent optimization of each layer's connectivity and latency characteristics while collectively achieving large coverage span through the stacked layers. The switch routes messages between layers based on identifier matching, enabling scalable architecture without proportionally increasing latency.
2Quantity of substance
If memory pools are scaled to accommodate diverse application needs, then the memory capacity increases, but the routing complexity increases
Solution Approach 1:
The patent changes the routing parameter from traditional address-based routing to identifier-based routing. Each memory node is assigned a unique identifier (such as port identifier or node identifier) that simplifies the routing decision process. The switch compares the destination identifier in incoming messages with its routing table to determine the next hop, regardless of the message content or memory address being accessed. This parameter change enables scalable memory capacity while keeping routing logic simple and consistent.
Solution Approach 2:
The switch acts as an intermediary that simplifies routing complexity by implementing identifier-based forwarding. Instead of requiring end systems to understand the complex topology of the entire memory pool, the switch mediates routing decisions by matching destination identifiers with routing table entries. This intermediary approach abstracts the underlying complexity, allowing memory capacity to scale while routing remains manageable through standardized identifier matching procedures.
Data Source
AI summary
A system including: a first memory layer including: a first memory node of a memory pool; and a second memory node of the memory pool, the second memory node being connected to the first memory node by one link in the first memory layer; and a switch to provide access to the first memory node from the second memory node based on: a first identifier corresponding to the first memory layer; and a second identifier corresponding to a location of the first memory node in the memory pool.