Memory Port Controller Push Mechanism for QoS Priority
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory transaction management systems face challenges in effectively prioritizing and handling high-priority Quality of Service (QoS) transactions, leading to inefficiencies and delays in completing higher-priority tasks due to the presence of lower-priority transactions in the pipeline.
Innovation Solution
A memory port controller is implemented to manage transactions by 'pushing' lower-priority transactions when a high-priority QoS transaction is received, ensuring that higher-priority transactions are completed quickly by treating lower-priority transactions as high priority and maintaining a count of outstanding high-priority transactions to facilitate efficient processing across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lower-priority transactions are allowed to proceed through the memory pipeline, then the memory system maintains continuous operation and resource utilization, but high-priority QoS transactions experience delays and cannot be completed promptly
Solution Approach 1:
The system dynamically adjusts the priority treatment of transactions in the pipeline based on the arrival of high-priority QoS transactions. When a high-priority transaction is detected, the memory port controller dynamically changes the processing mode from normal FIFO ordering to push mode, where subsequent lower-priority transactions are pushed forward and treated as high-priority. This dynamic adaptation resolves the contradiction by allowing the system to maintain QoS guarantees when needed while preserving normal continuous operation during standard conditions.
Solution Approach 2:
The system performs preliminary actions by maintaining a count of outstanding high-priority QoS transactions and proactively pushing lower-priority transactions before they complete processing. By anticipating the need to clear the pipeline for high-priority transactions and performing the push action in advance, the system ensures that high-priority transactions can be completed promptly without waiting for lower-priority transactions to naturally complete, thus resolving the time delay issue while maintaining QoS reliability.
2Productivity
If the memory port controller pushes lower-priority transactions to make way for high-priority QoS transactions, then high-priority transaction completion is improved, but the complexity of transaction management and coordination increases
Solution Approach 1:
The system employs feedback mechanisms where the memory port controller monitors the arrival of high-priority QoS transactions and the completion status of pushed transactions. The controller receives feedback about outstanding high-priority transactions and adjusts its pushing behavior accordingly. This feedback loop enables the system to improve high-priority transaction throughput through intelligent pushing while managing complexity by using automated monitoring and control rather than manual or overly complex arbitration mechanisms.
Solution Approach 2:
The memory port controller acts as an intermediary between the coherency port and the memory system, mediating the conflicting requirements of high-priority and low-priority transactions. It introduces a push control mechanism that coordinates transaction flow, counting outstanding high-priority transactions and selectively pushing lower-priority transactions. This intermediary approach improves high-priority throughput while containing complexity by localizing the control logic to a single coordination point rather than distributing complexity throughout the entire memory subsystem.
3Speed
If multiple clock domains are used for different memory components, then each component can operate at optimal speeds, but coordinating transaction pushing across clock domains becomes more difficult
Solution Approach 1:
The memory port controller serves as a clock domain intermediary, receiving high-priority transaction signals from the coherency port controller in one clock domain and coordinating the pushing of transactions to the memory system in another clock domain. It maintains a count of outstanding high-priority transactions and uses this information to trigger push operations at the appropriate moments, bridging the timing differences between clock domains. This intermediary approach enables each component to operate at its optimal speed while managing clock domain coordination complexity through centralized timing control.
Data Source
AI summary
In an embodiment, a memory port controller (MPC) is coupled to a memory port and receives transactions from processors and a coherency port (ACP) used by one or more peripheral devices that may be cache coherent. The transactions include various quality of service (QoS) parameters. If a high priority QoS transaction is received on the ACP, the MPC may push previous (lower priority) transactions until the high priority transaction may be completed. The MPC may maintain a count of outstanding high priority QoS transactions. The L2 interface controller and ACP controller may push increment and decrement events based on processing the high priority QoS transactions, and the MPC may push the memory transactions when the count is non-zero. In an embodiment, the MPC may continue pushing transactions until the L2 interface controller informs the MPC that the earlier transactions have been completed.