Memory Port Segmentation for High Bandwidth
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Solution Overview
Problem
Current DRAM designs that share the same port for row and column address signals lead to inefficiencies, such as incomplete data line occupation and reduced memory speed, especially in high-bandwidth applications, due to the need for pre-fetch and burst techniques, which can cause data wastage and poor flexibility.
Innovation Solution
Separating row and column address ports allows for simultaneous transmission of address signals, ensuring the data line is always fully occupied by enabling continuous data transmission without waiting for read commands to finish, thereby improving memory speed and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If row and column address ports are shared, then device complexity is reduced, but memory speed and data transmission efficiency deteriorate
Solution Approach 1:
The command port is segmented into two independent sub-ports: a row address port (RAS) and a column address port (CAS). This segmentation allows simultaneous reception of row and column address signals without mutual interference, resolving the bottleneck where sequential address transmission limited memory speed. The segmentation maintains relatively simple device architecture while significantly improving data transmission efficiency.
2Duration of action of moving object
If pre-fetch and burst techniques are used, then data transmission continuity is improved, but data line occupation efficiency deteriorates due to data wastage
Solution Approach 1:
The memory system dynamically receives row and column address signals at different times through separate ports, enabling flexible timing control without being constrained by fixed pre-fetch or burst patterns. This dynamic approach allows the data line to be occupied continuously with valid data only, eliminating the data wastage inherent in static pre-fetch and burst techniques while maintaining transmission continuity.
Data Source
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AI summary
A memory includes a memory chip (100), a command port (102) and a data port (103). The memory chip (100) includes at least one channel (10). Each channel (10) includes a plurality of banks (101), and the banks (101) are configured to perform read and write operations alternately. The command port (102) is configured to receive command signals at a preset edge of a command clock, and the command signals are configured to control the read and write operations of the banks (101). The data port (103) is configured to receive data signals to be written into the banks (101) or transmit data signals at preset edges of a data clock. The command port (102) includes a row address port (112) and a column address port (122). The row address port (112) is configured to receive a row address signal at a position of a target memory cell, and the column address port (122) is configured to receive a column address signal at a position of the target memory cell.