Embedded Memory Power Circuit Segmentation

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Solution Overview

Problem

The increasing miniaturization of transistors in cache memories leads to higher leakage currents during standby, resulting in increased power consumption, decreased signal-to-noise margins, and slower memory operations.

Innovation Solution

Implementing a power circuit that selectively couples memory cell buses to different power planes, adjusting bit line voltages, and using pre-charge circuits to manage power consumption and maintain signal integrity during reduced power states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If transistor feature sizes are decreased to increase memory density, then memory capacity increases, but leakage current during standby increases leading to higher power consumption

Engineering Contradiction:

Improvememory capacityVSAvoidpower consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The memory array is divided into multiple banks, and the power circuit selectively couples only the active bank to the first power plane while keeping other banks coupled to the second power plane or in a high-impedance state. This segmentation allows different portions of the memory to operate at different power states simultaneously, reducing overall standby power consumption while maintaining required memory capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The power circuit dynamically switches between coupling memory cell buses to the first power plane (full power operation) and the second power plane (reduced power operation) based on activity requirements. This dynamic power management allows the system to adapt power consumption to actual operational needs, reducing leakage current during standby while maintaining performance during active operations.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If power consumption is reduced during standby, then energy efficiency improves, but signal-to-noise margins decrease leading to more errors

Engineering Contradiction:

Improvepower consumptionVSAvoidsignal-to-noise margin

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The pre-charge circuit proactively charges bit lines to appropriate voltage levels before memory access operations. By pre-charging bit lines during the transition to the first power plane, the system ensures that signal levels are established before read operations begin, maintaining adequate signal-to-noise margins even when transitioning from reduced power states. This preliminary action prevents errors that would otherwise occur due to insufficient signal margins during power state transitions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The pre-charge circuit acts as an intermediary between the power circuit and the bit lines, mediating the transition between power states by ensuring proper voltage levels are established on bit lines before memory operations. This intermediary function isolates the impact of power state changes from the actual memory read/write operations, maintaining signal integrity and noise margins during transitions.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Use of energy by moving object

If power is reduced to memory cell buses, then standby power consumption decreases, but memory operation speed decreases

Engineering Contradiction:

Improvepower consumptionVSAvoidmemory operation speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The system periodically transitions memory banks between reduced power state (coupled to second power plane) and full power state (coupled to first power plane) based on access patterns. By using periodic action, the system can allow memory operations to complete at full speed when needed while spending more time in the reduced power state, achieving an overall reduction in power consumption without permanently degrading operation speed.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

Inventive Principle:

Principle #15Dynamics

4Use of energy by moving object

If conventional power-saving methods are used, then power consumption reduces, but memory size increases and performance degrades

Engineering Contradiction:

Improvepower consumptionVSAvoidmemory size

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The power circuit and pre-charge circuit are designed to serve multiple functions: they enable both full-power and reduced-power operation modes, support multiple memory banks, and provide seamless transitions between power states. This multi-functionality allows the same hardware infrastructure to achieve power savings without requiring additional memory capacity or significantly increasing overall system complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8243541B2Methods and apparatuses for improving reduced power operations in embedded memory arrays

Publication Date: 2012.08.14 ORACLE AMERICAN INC

AI summary

Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively coupling the memory cell bus to a first power plane and a second power plane, where the memory cell bus is coupled to the second power plane when the power circuit is substantially off, and a bit line pre-charge circuit coupled to the power circuit, where the power circuit selectively couples the first power plane to the pre-charge circuit for a predetermined period of time.