Memory Power Control via Pre-loaded Mode Register Sequencing
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Solution Overview
Problem
Existing DDR DRAM systems face significant overhead in terms of time when executing power state change requests due to the need to re-program multiple mode registers, especially as systems become more complex with deep memory hierarchies.
Innovation Solution
A data processor and memory controller system that includes a memory operation array, a power engine, and an initialization circuit, which allows for efficient power state changes by sequencing memory operations to meet the minimum timing parameter tMRW, thereby reducing channel stalling and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If mode registers are re-programmed to change power states in complex DDR DRAM systems, then power state changes can be executed, but significant time overhead is incurred due to the number of mode registers that must be re-programmed
Solution Approach 1:
The patent pre-loads configuration data for multiple power states into a buffer memory before actual power state changes are needed. This preliminary action stores mode register settings, timing parameters, and other configuration data in advance, so that when a power state transition is requested, the pre-configured data can be quickly retrieved and applied without performing time-consuming programming operations at the moment of transition.
Solution Approach 2:
The patent divides the power state change process into separate independent stages: configuration data preparation, buffer loading, and actual mode register programming. By segmenting the mode register programming into individual bank operations that can be performed in parallel, and separating the time-consuming data preparation from the execution phase, the system reduces the critical path time for power state transitions.
2Adaptability or versatility
If multiple mode registers are programmed sequentially to support deep memory hierarchies, then complex memory configurations are supported, but channel stalling increases and efficiency decreases
Solution Approach 1:
The patent segments the memory banks into independent units that can be configured separately. Each bank's mode registers can be programmed independently and in parallel, rather than requiring sequential programming of all registers across all banks. This segmentation allows the memory controller to divide the configuration task into smaller chunks that can be executed concurrently, reducing total configuration time and minimizing channel stalling.
Solution Approach 2:
The patent merges the configuration data for multiple banks and mode registers into a single unified buffer structure. This allows the memory controller to retrieve and issue configuration commands for multiple banks simultaneously, combining what would otherwise be separate sequential operations into a single parallel execution stream, thereby improving efficiency while supporting complex memory hierarchies.
3Adaptability or versatility
If DDR DRAM systems are made faster and more complex to support additional features, then functionality increases, but the number of mode registers that must be re-programmed grows
Solution Approach 1:
The patent pre-configures and stores the settings for all mode registers in a buffer memory during system initialization or before power state transitions. This preliminary preparation captures the complexity of programming multiple mode registers in advance, organizing the configuration data for numerous registers, timing parameters, and control settings into a structured format that can be quickly applied without requiring complex real-time processing when power states need to change.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the memory controller and the mode registers. This buffer acts as a mediator that holds pre-prepared configuration data, allowing the controller to manage complex multi-register programming operations without directly handling each register individually. The buffer absorbs the complexity of coordinating multiple register writes, timing requirements, and bank-specific configurations, simplifying the controller's task while supporting enhanced device functionality.
Data Source
AI summary
A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory operations are separated by an amount corresponding to a predetermined minimum timing parameter.