Memory Power Controller for Data Center Energy Reduction

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Solution Overview

Problem

Computer servers in data centers consume high power even during low utilization periods due to continuous power requirements for memory components like DIMMs, leading to increased operational costs and energy inefficiency.

Innovation Solution

A system comprising a power controller and a management controller that monitors memory utilization levels and selectively disables power to unused memory components during low utilization periods, using MOSFETs to manage power distribution and a programmable logic device to execute power-saving commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory components are continuously powered to ensure rapid access for processors, then memory access speed and reliability are maintained, but power consumption increases during low utilization periods

Engineering Contradiction:
Improvememory access reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the power state of memory components based on real-time utilization monitoring. The management controller transitions memory from a powered-on state during high utilization to a powered-off state during low utilization, making the power delivery adaptive to actual workload conditions rather than static

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The management controller predicts low utilization periods based on historical data and patterns, proactively powering down memory components before the actual low utilization period begins. This preliminary action ensures memory is already in the low-power state when utilization drops, maximizing energy savings while maintaining rapid response capability

Inventive Principle:
Principle #10Preliminary action

2Speed

If all memory components remain powered on to support potential processor demands, then system responsiveness is maintained, but operational costs increase due to continuous power consumption

Engineering Contradiction:
Improvesystem responsivenessVSAvoidoperational cost
Core Design Contradiction:
SpeedVSUse of energy by stationary object

Solution Approach 1:

The system segments the memory subsystem into individually controllable power domains. Instead of powering all memory components uniformly, the management controller can selectively power down specific memory modules or banks that are not currently being accessed, while keeping other segments active to maintain system responsiveness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the power delivery parameter from a constant high state to a variable state that adjusts based on utilization. During low utilization periods, the power voltage or current to memory components is reduced or eliminated entirely, directly lowering operational costs while maintaining the capability to rapidly restore full power when needed

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power consumption by powering down unnecessary memory components during low utilization periods, thereby conserving energy and lowering operational costs in data centers.

Implementation Method 1

A system to save power in a computer system includes a power controller controlling connection of power to each of a plurality of memory components

Methodology Applied
Scientific EffectMOSFET switching: Electrical Resistance

Data Source

PatentUS12079062B2Method and system for providing power saving in computer systems
Publication Date: 2024.09.03 QUANTA COMPUTER INC
  • US12079062B2 patent drawing
  • US12079062B2 patent drawing
  • US12079062B2 patent drawing

AI summary

A system and method to save power in a computer system is disclosed. The system includes a power controller controlling connection of power to each of a plurality of memory components. A processor is coupled to the memory components. The processor operates with varying utilization levels of the memory components. A management controller is coupled to the processor and the power controller. The management controller determines a period of low utilization based on memory utilization data from the processor. The management controller commands the power controller to disable power to some of the plurality of memory components during the period of low utilization.