Memory Controller Power Domains for Fast Wake-Up From Low Power
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Solution Overview
Problem
Existing power management standards like ACPI do not optimize power consumption or performance of specific data processing systems, and existing memory controllers lack efficient mechanisms for transitioning between power states to enhance power savings and performance.
Innovation Solution
A memory controller with a local power state controller and isolation cells that allow for independent power management of voltage domains, enabling rapid transitions between power states by saving configuration and state data in on-chip SRAM, and maintaining the DRAM PHY in a low-power state during controller downtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory controller is completely powered down to save power, then power consumption is reduced, but the system experiences high latency when waking up due to PHY reconfiguration
Solution Approach 1:
The memory controller is divided into separate power domains: the logic core can be fully powered down while the DRAM PHY operates in a separate low-power state. This segmentation allows independent power management of different functional blocks, enabling the logic core to enter deep power savings mode without completely shutting down the PHY, thus reducing wake-up latency while maintaining power savings.
Solution Approach 2:
The DRAM PHY is maintained in a low-power state with configuration data preserved in on-chip SRAM before the logic core is powered down. This preliminary preparation of the PHY state and configuration data allows for rapid resume operation when the logic core wakes up, significantly reducing the wake-up latency that would otherwise occur due to PHY reconfiguration.
2Use of energy by moving object
If the memory controller enters a deep power-down state to maximize power savings, then energy consumption is reduced, but system response time deteriorates due to reconfiguration overhead
Solution Approach 1:
By segmenting the memory controller into independently power-managed domains (logic core and DRAM PHY), the system can achieve deep power savings in the logic core while keeping the PHY in a responsive low-power state. This segmentation resolves the contradiction by allowing maximum power savings without sacrificing system response time, as the PHY can quickly resume operations without full reconfiguration.
Solution Approach 2:
The system changes the power state parameters of different components differently: the logic core transitions to a deep power-down state for maximum savings, while the DRAM PHY transitions to a low-power state that maintains operational readiness. This differential parameter change allows the system to optimize both power consumption and response time simultaneously.
3Adaptability or versatility
If ACPI power management is used to control device power modes, then standardized power control is achieved, but specific optimization for memory controller performance and power consumption is lost
Solution Approach 1:
The memory controller implements self-service power management through its local power state controller that autonomously manages the PHY power state and configuration data storage in on-chip SRAM. This self-service mechanism allows the memory controller to optimize its own power consumption and performance without relying solely on generic ACPI commands, achieving both standardization compliance and device-specific optimization.
Solution Approach 2:
The local power state controller acts as an intermediary between the ACPI power management interface and the DRAM PHY power state control. It translates standardized ACPI power requests into optimized, device-specific power state transitions for the PHY, maintaining compatibility with ACPI while enabling tailored optimization for the memory controller's power and performance characteristics.
Data Source
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AI summary
A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.