Memory Power Estimation Using Wrapper Models for SoC Testing
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Solution Overview
Problem
Conventional methods for estimating power consumption of memory components during testing are resource-intensive and impractical for large-scale circuit designs like SoCs, often requiring extensive simulations and large value change databases, making them inefficient and costly.
Innovation Solution
Generate wrappers for memory library cells, determine toggle and probability values for each pin, and use these to estimate power consumption early in the design flow, avoiding extensive simulations and VCDs, enabling parallel estimation across multiple memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional simulation methods are used to estimate power consumption, then measurement precision is improved, but device complexity and computational resources increase significantly
Solution Approach 1:
The patent creates simplified wrapper models that replicate the essential power consumption characteristics of memory cells without requiring full-scale circuit simulations. These wrapper models copy only the necessary behavioral properties needed for power estimation, eliminating the need for complex value change databases and extensive simulation resources while maintaining sufficient accuracy for power grid design decisions.
Solution Approach 2:
The patent employs lightweight wrapper models that are computationally inexpensive to generate and evaluate. These wrappers are designed to be quickly created and discarded after providing their power estimation function, replacing the need for expensive, long-running conventional simulations. The wrappers use simplified calculations based on toggle rates and activity factors rather than full circuit state tracking.
2Measurement precision
If extensive simulations and large value change databases are used, then power consumption estimation accuracy is improved, but productivity and design flow efficiency deteriorate
Solution Approach 1:
The patent performs power consumption estimation early in the design flow using wrapper models before detailed circuit implementation and timing closure. This preliminary action allows power grid design decisions to be made earlier, avoiding iterative redesign cycles later in the process. The wrapper models can be instantiated and evaluated without waiting for complete circuit simulation data or value change databases to be generated.
3Loss of time
If parallel memory testing is implemented, then test time is reduced, but power consumption during testing increases
Solution Approach 1:
The patent uses wrapper models with configurable parameters such as toggle rates and activity factors that can be adjusted to reflect different testing scenarios. By modifying these parameters, the model can estimate power consumption for various parallel testing configurations, allowing designers to evaluate and optimize test schedules to balance test time reduction against power consumption increases.
Data Source
AI summary
Various embodiments provide for estimating power consumption by one or more memory components of a circuit design during memory testing, which can be used as part of an electronic design automation (EDA) software.