Semiconductor Memory Power Feed Cell Layout Area Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing the layout area of power feed cells, leading to increased layout area of the entire memory array due to the need for piling regions and interconnection tracks, which interferes with bit lines and power supply lines.
Innovation Solution
The semiconductor memory device incorporates a power feed cell layout where the first power supply line is coupled to the first well region through a contact in the first metal interconnection layer, and the second power supply line is formed in an upper layer, electrically coupled to the second well region through multiple contacts, eliminating the need for a piling region and reducing the layout area of the power feed cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If well feed is performed individually for each memory cell, then power supply reliability is improved, but layout area increases due to interconnection regions
Solution Approach 1:
The patent merges the well feed function into shared power feed cells that serve multiple memory cells simultaneously. Instead of providing individual well feed connections to each memory cell, a single power feed cell with shared N well and P well regions supplies power to multiple memory cell columns, reducing the total interconnection area while maintaining power supply reliability through the shared structure.
2Ease of operation
If power feed cell layout includes separate power supply lines for N well and P well, then power supply control is improved, but layout area increases due to piling regions
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by forming power supply lines in different metal layers. The first power supply line (for N well) is formed in a first metal layer, while the second power supply line (for P well) is formed in a second metal layer above it. This vertical stacking eliminates the need for lateral piling regions, allowing both power supply lines to coexist without increasing layout area, while maintaining independent power supply control for N well and P well regions.
Data Source
AI summary
A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a P well voltage is provided in a third metal interconnection layer. The metal supplying the N well voltage is formed using a metal in the first metal interconnection layer and thus does not require a piling region to the underlayer, and only a piling region to the underlayer of the metal for the P well voltage needs to be secured. Therefore, the length in the Y direction of a power feed cell can be reduced thereby reducing the layout area of the power feed cell.