Semiconductor Memory Power Gating via Controller

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Solution Overview

Problem

As semiconductor memory devices increase in capacity and number of dies, power consumption also increases proportionally, leading to inefficient energy use in mobile devices.

Innovation Solution

A semiconductor memory device with a controller that independently supplies or blocks power to each unit or package, using a power management integrated circuit (PMIC) with transistors and power gating elements to manage power distribution, allowing for selective activation of only necessary units to minimize power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the capacity and number of dies in semiconductor memory device are increased, then the memory capacity is improved, but the power consumption increases

Engineering Contradiction:
Improvememory capacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The memory device is divided into multiple independently controllable units or dies. The controller can selectively activate or deactivate specific units based on the required memory capacity, allowing power consumption to be optimized by only activating necessary portions rather than the entire memory device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The power supply to each memory unit is dynamically controlled through individual power gating signals. The controller adjusts which units receive power based on real-time memory capacity requirements, enabling the system to adapt power consumption to actual operational needs rather than maintaining static power supply to all units.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If power is supplied to all units in semiconductor memory device, then the available memory capacity is improved, but unnecessary power consumption occurs in unused units

Engineering Contradiction:
Improveavailable memory capacityVSAvoidunnecessary power consumption
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

Instead of supplying power to all memory units simultaneously, the system supplies power only to the specific units needed for the current operation. This partial action approach ensures that power is consumed only where necessary, eliminating waste while maintaining full memory capacity availability when needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

Each memory unit has its own power gating control that allows it to be independently activated or deactivated. This self-service capability enables the memory system to automatically adjust power distribution based on operational requirements without requiring external intervention for each unit.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient power management by blocking power to unused units, reducing unnecessary consumption and optimizing energy use based on device requirements, thereby extending battery life and improving performance in mobile devices.

Implementation Method 1

a power management integrated circuit (PMIC) including a plurality of transistors connected to the semiconductor device via a plurality of power lines and configured to provide power to the semiconductor device through the plurality of power lines

Methodology Applied
Scientific EffectPower gating: Electrical Resistance

Data Source

PatentUS10664333B2Semiconductor memory device including a controller for controlling power and electronic device including the semiconductor memory device
Publication Date: 2020.05.26 SAMSUNG ELECTRONICS CO LTD
  • US10664333B2 patent drawing
  • US10664333B2 patent drawing
  • US10664333B2 patent drawing

AI summary

A semiconductor memory device includes a memory including a plurality of units, and a controller. Under control of the controller, a power for an operation of the memory is independently supplied to each of the plurality of units or is independently blocked with respect to each of the plurality of units. Each of the plurality of units may be one of a package, die, or chip. A supply of the power to at least a part of the plurality of units, to which the power is supplied, may be blocked under control of the controller. Accordingly, unnecessary power consumption may be prevented. Furthermore, power may be additionally supplied to at least a part of the plurality of units to which the power is not supplied, under control of the controller, and these units may be initialized.