Memory Device Power Line Layout for Sense Amplifier Stability
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Solution Overview
Problem
As semiconductor memory devices shrink in size, the layout area for sense amplifiers decreases, making it difficult to implement the power and signal line configuration, especially with increasing global data input/output lines, which complicates the top layout and makes it challenging to ensure stable power and signal supply.
Innovation Solution
The memory device layout is simplified by reducing the number of power lines over the sense amplifier region by configuring power lines to cross over sub-memory cell arrays and sense amplifiers in a specific alternating pattern, allowing power lines to be disposed on both sides of global data input/output lines, thereby simplifying the layout and maintaining stable power and signal supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of global data input/output lines is increased, then the data input/output capability is improved, but the layout complexity of the sense amplifier region becomes excessive
Solution Approach 1:
The sense amplifier region is divided into first and second regions with different power line configurations. The first region has power lines on both sides of global data input/output lines, while the second region has power lines only on one side. This segmentation allows the layout to handle increased data lines without excessive complexity throughout the entire region.
Solution Approach 2:
Different areas of the sense amplifier region are assigned different power line arrangements based on local requirements. Regions requiring stable power supply for sense amplifiers have power lines on both sides, while other regions use single-side power lines. This local differentiation optimizes the layout for increased data throughput without uniformly increasing complexity.
2Area of moving object
If the device size is reduced, then the integration density is improved, but the power and signal line configuration becomes difficult to implement
Solution Approach 1:
The reduced device area is managed by segmenting the sense amplifier region into first and second regions with different power line configurations. This segmentation allows efficient use of limited space while maintaining manufacturable power and signal line arrangements.
Solution Approach 2:
The patent transitions from a uniform two-dimensional power line arrangement to a segmented arrangement that effectively utilizes vertical spacing and regional differentiation. By assigning different power line configurations to different regions, the design accommodates reduced device area while preserving configuration feasibility.
3Reliability
If power lines are disposed on both sides of global data input/output lines, then the stable power supply is ensured, but the layout complexity increases
Solution Approach 1:
Power lines are disposed on both sides of global data input/output lines only in the first region where sense amplifiers require stable power supply. In the second region, power lines are disposed on one side only. This local quality approach ensures power supply stability where needed while reducing layout complexity in other areas.
Solution Approach 2:
The sense amplifier region is segmented into first and second regions with different power line configurations. The first region uses dual-side power lines for stable power supply, while the second region uses single-side power lines to reduce complexity. This segmentation resolves the contradiction between reliability and complexity.
Data Source
AI summary
A memory device and method for arranging signal and power lines includes a plurality of sub-memory cell arrays having a plurality of memory cells, a plurality of sense amplifiers to sense and amplify data from the plurality of memory cells, a plurality of power lines to provide power to the sense amplifiers, where at least one of the power lines is disposed over a first set of the sense amplifiers and the sub-memory cell arrays, and at least another one of the power lines is disposed over second set of the sense amplifiers and the sub-memory cell arrays.