Memory Power Loss Detection Using Partial Block Voltage Offsets
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Solution Overview
Problem
Existing power loss error detection procedures in memory devices, particularly in multi-level cells (MLCs), result in a high overkill rate due to shifts in threshold voltages caused by phenomena like back-pattern effects and cell-to-cell coupling, leading to unnecessary power, computing, and memory resource consumption.
Innovation Solution
Implementing a power loss error detection procedure that compensates for partial block-induced voltage shifts by using word line group and partial block fill ratio-dependent offsets, allowing for more accurate determination of programming completion and reliability margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power loss error detection procedures are used in multi-level cells, then error detection capability is provided, but the overkill rate increases due to threshold voltage shifts from back-pattern effects and cell-to-cell coupling
Solution Approach 1:
The patent applies parameter changes by adjusting the read reference voltage based on the programmed data pattern. Specifically, when a partial block is detected (indicated by a first bit pattern), the read reference voltage is shifted by a predetermined offset amount. This dynamic parameter adjustment compensates for threshold voltage shifts caused by back-pattern effects and cell-to-cell coupling, enabling accurate error detection without unnecessary power consumption.
Solution Approach 2:
The patent implements dynamics by making the read reference voltage adaptive rather than fixed. The reference voltage dynamically changes based on the detected bit pattern in the partial block. When the first bit pattern indicating partial block programming is detected, the system automatically adjusts the reference voltage to account for voltage shifts, thereby reducing false positives and the associated power waste.
2Reliability
If traditional power loss error detection procedures are used, then programming completion detection is attempted, but computing resources are wasted due to high overkill rate
Solution Approach 1:
The patent changes the parameter of read reference voltage based on the detected bit pattern. When a partial block is identified through the first bit pattern, the reference voltage is adjusted by a predetermined offset. This parameter change enables more accurate determination of programming completion status, reducing false detections and the associated computing resource waste.
Solution Approach 2:
The patent employs feedback by using the detected bit pattern from the partial block to adjust the read reference voltage for subsequent read operations. This feedback mechanism ensures that the error detection procedure adapts to the actual programming conditions, improving accuracy and reducing unnecessary computational overhead.
3Reliability
If traditional power loss error detection procedures are used, then memory resource consumption is monitored, but memory resources are wasted due to unnecessary operations
Solution Approach 1:
The patent adjusts the read reference voltage parameter based on the bit pattern detected in the partial block. When the first bit pattern indicating partial block programming is detected, the reference voltage is shifted by a predetermined offset. This parameter adjustment improves error detection accuracy by accounting for threshold voltage shifts, thereby preventing unnecessary memory operations and resource consumption.
Solution Approach 2:
The patent applies partial action by focusing the error detection procedure on the specific partial block that was programmed, rather than unnecessarily scanning the entire memory block. By detecting the first bit pattern and adjusting the reference voltage accordingly, the system performs targeted detection only where needed, reducing memory resource consumption while maintaining reliability.
Data Source
AI summary
In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.