Hierarchical Memory Power Management for Artificial Reality
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Solution Overview
Problem
Artificial reality systems face challenges in managing power consumption of memory, leading to reduced battery life and decreased responsiveness due to inefficient power management techniques, particularly in devices like head-mounted displays and peripherals that require fine-grained control over memory power modes.
Innovation Solution
The implementation of a hierarchical power management system using RAM domain controllers (RDCs) and RAM domain blocks (RDBs) that provide both hardware and software control over memory blocks, allowing for fine-grained power control and independent operation of memory blocks in different power modes, reducing power consumption and improving latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory blocks operate in high power mode to ensure fast access and responsiveness, then system responsiveness is improved, but power consumption increases reducing battery life
Solution Approach 1:
The memory system is divided into multiple independently controllable memory blocks, each capable of operating in different power modes. The RAM domain controller separately controls the power mode of each memory block based on access requirements, allowing frequently accessed blocks to remain in high power mode while less accessed blocks enter low power mode, thus resolving the contradiction between speed and power consumption.
Solution Approach 2:
The system dynamically transitions memory blocks between different power modes (high power mode for fast access, low power mode for power saving) based on real-time access patterns. The RAM domain controller monitors access requirements and adjusts power modes accordingly, making the system adaptive to changing workload demands and resolving the static trade-off between speed and power consumption.
2Use of energy by moving object
If memory blocks are placed in low power mode to extend battery life, then power consumption is reduced, but system responsiveness deteriorates due to access latency
Solution Approach 1:
The system proactively places memory blocks into low power mode when access is not required, preparing for power savings in advance. When access is needed, the RAM domain controller quickly transitions the block back to high power mode, minimizing the impact on responsiveness while maximizing power savings during idle periods.
Solution Approach 2:
Different memory blocks are assigned different power modes based on their specific access patterns and requirements. Frequently accessed blocks maintain high power mode for fast access, while less accessed blocks enter low power mode for power savings, allowing the system to optimize the balance between power consumption and access latency on a block-by-block basis.
3Measurement precision
If fine-grained control over individual memory blocks is implemented, then power management precision is improved, but system complexity increases
Solution Approach 1:
The RAM domain controller serves as an intermediary between the memory blocks and the power management system. It centralizes the control logic for managing power modes of multiple memory blocks, simplifying the overall system architecture while enabling fine-grained control. The controller handles the complexity of individual block management, allowing precise power control without proportionally increasing overall system complexity.
Data Source
AI summary
The disclosure describes techniques for hierarchical power management of memory of an artificial reality system to reduce power consumption by the memory. An example device may be a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content for display. The device includes memory divided into multiple memory blocks configurable to operate in a plurality of power modes. The device also includes memory block controllers controlling memory blocks. Each memory block controller controls which power mode in which the corresponding memory block is to operate, independent of any of the other memory blocks. The device includes a memory power controller configured to configure control registers of the memory block controllers to direct the memory block controllers to select one of the plurality of power modes for the memory blocks when the memory blocks are not being accessed.