Memory Power Management via Segmented Charge Pumps
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Solution Overview
Problem
Conventional memory systems face challenges with large die sizes due to high power requirements and heat generation, complex circuitry, and limited driving voltage capabilities, which lead to memory system failures and increased manufacturing and operational costs.
Innovation Solution
Implementing non-volatile third dimension memory arrays coupled with multiple, smaller charge pumps to reduce die size, enable reduced power requirements, and facilitate faster, simultaneous programmable sequences without increasing die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If conventional charge pumps are used to generate large output voltages, then driving voltage capability is improved, but die size increases due to larger capacitors
Solution Approach 1:
The patent divides the memory array into multiple banks, each with its own smaller charge pump. This segmentation allows each charge pump to serve a limited region, reducing the capacitor size needed while maintaining adequate driving voltage capability for its designated bank.
Solution Approach 2:
The patent transitions from a two-dimensional planar charge pump design to a three-dimensional stacked architecture where charge pumps are vertically integrated with memory banks. This dimensional change increases functional density without proportionally increasing die area.
2Adaptability or versatility
If conventional circuit patterns are used to accommodate multiple processors and buffer memory, then functionality is improved, but die size increases
Solution Approach 1:
The patent merges the memory array and controller logic into a single integrated device. The controller is directly coupled to the memory array without requiring separate buffer memory or external processors, combining multiple functions into one compact unit.
Solution Approach 2:
The memory device is designed to perform multiple functions including data storage, error detection, and error correction within a single integrated structure. The same memory cells serve both as storage elements and as part of the error correction mechanism through redundant bit storage.
3Stability of the object's composition
If conventional charge pumps with large capacitors are used, then voltage stability is improved, but power consumption increases
Solution Approach 1:
By segmenting the memory system into multiple banks with dedicated smaller charge pumps, each pump only needs to maintain voltage stability for its local bank rather than the entire array. This reduces the capacitor size and associated power consumption while maintaining adequate voltage stability for each segment.
Solution Approach 2:
The patent changes the operating parameters by using multiple charge pumps operating in parallel at lower individual capacities rather than a single large charge pump. This parameter change allows each pump to use smaller capacitors with lower power requirements while collectively providing sufficient voltage stability across the entire memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced die size, lower power consumption, and improved access times for memory systems while maintaining or enhancing functionality, thereby reducing fabrication and operational expenses and minimizing errors.
Implementation Method 1
Charge pumps may be used to receive an input voltage, transfer power using one or more capacitors, and generate an output or driving voltage that is larger or smaller than the input voltage
Data Source
AI summary
Memory power management is described. A non-volatile memory array is provided, the array including separately controlled memory blocks. At least two charge pumps are coupled to the array, the charge pumps being configured to provide at least two voltages. Logic is configured to control how the voltages are delivered to the memory blocks.