Memory Power Management for Electronic Paper Updates

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Solution Overview

Problem

Conventional data processing devices with electronic paper displays face challenges in reducing power consumption during active operation, as they require continuous memory access for updating, preventing the use of power-saving modes and leading to increased overall power consumption due to the longer drawing time of electronic paper compared to LCDs.

Innovation Solution

A data processing device structure that includes a SoC, non-volatile main memory, and a power management system, where update-data is divided and copied to internal memory buffers, allowing the main memory to be powered off during idle periods, while the internal memory remains active for updating, thereby reducing overall power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If continuous memory access is performed during electronic paper updating, then updating can proceed without interruption, but power consumption of the memory cannot be reduced

Engineering Contradiction:
Improveupdating timeVSAvoidmemory power consumption
Core Design Contradiction:
Duration of action of moving objectVSUse of energy by moving object

Solution Approach 1:

The patent divides the updating process into multiple segments by dividing update-data into a plurality of divided data and performing updating processes in sequence. This segmentation allows the memory to be accessed only during specific segments (when divided data is being written) rather than continuously, enabling power-saving modes during idle segments between updates.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic action by alternating between updating processes and idle periods where the memory can enter power-saving modes. The control device manages periodic cycles of: writing divided data to the memory, waiting for the updating process to complete, and then repeating the cycle with the next divided data, thereby creating regular intervals for power management.

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If the memory is powered off during idle periods, then power consumption is reduced, but updating process may be delayed

Engineering Contradiction:
Improvememory power consumptionVSAvoidupdating delay
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by dividing and preparing update-data before the updating process begins. The control device divides the update-data into multiple divided data portions and can write them to the memory in advance or in a staged manner, so that when the memory is powered off during idle periods, the system is already prepared with pre-processed data, minimizing the impact of power-saving interruptions on the overall updating timeline.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9304578B2Control device, data processing device, controller, method of controlling thereof and computer-readable medium
Publication Date: 2016.04.05 KIOXIA CORP
  • US9304578B2 patent drawing
  • US9304578B2 patent drawing
  • US9304578B2 patent drawing

AI summary

A control device according to embodiments comprises a data-copying unit, a data-processing instructing unit, and a power-control unit. The data-copying unit copies data in a first memory to a second memory of which power consumption is less than power consumption of the first memory. The data is to be processed at a first data processing unit. The data-processing instructing unit instructs the first data processing unit to process the data copied to the second memory. The power-control unit switches power for the first memory from a first power to a second power while the first data processing unit is processing the data copied to the second memory. The first power is power supplied to the first memory at a time when the data is copied from the first memory to the second memory. The second power is lower than the first power.