Memory Device Power Off Sequence Using Voltage Ramp Down
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Solution Overview
Problem
Existing memory devices face challenges in efficiently powering off while ensuring data retention, particularly in systems like DRAM and SDRAM, where rapid voltage changes can lead to data loss and hardware instability.
Innovation Solution
A ramp down technique is implemented, where a first voltage source is monitored for a pre-set threshold, triggering a sequence of events to pre-charge memory banks and ramp down internal voltages using a second voltage source, ensuring data retention and adhering to JEDEC specifications without requiring new power sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If voltage is rapidly reduced during power off, then power off speed is improved, but data retention deteriorates and hardware instability occurs
Solution Approach 1:
The patent applies preliminary action by pre-charging memory banks before the actual power off sequence. When a power off condition is detected, the system first activates pre-charge circuits to maintain voltage levels in memory cells, then gradually ramps down internal voltages using a second voltage source. This preliminary preparation ensures data is secured before voltage reduction begins, resolving the contradiction between fast power off and data retention.
2Productivity
If rapid voltage reduction is used during shutdown, then shutdown speed is improved, but hardware stability deteriorates
Solution Approach 1:
The system performs preliminary actions by detecting power off conditions and activating pre-charge circuits before initiating voltage ramp-down. This preparation phase ensures memory banks are properly charged and ready to maintain data during the subsequent controlled voltage reduction, preventing hardware instability while maintaining efficient shutdown speed.
Solution Approach 2:
The patent implements dynamics by using a controlled ramp-down sequence for internal voltages rather than abrupt cutoff. A second voltage source gradually reduces voltage levels over time, allowing circuits to adapt smoothly to changing conditions. This dynamic approach maintains hardware stability during shutdown while still achieving relatively fast power off compared to traditional methods.
3Reliability
If pre-charge sequence is implemented before power off, then data retention is improved, but power off time increases
Solution Approach 1:
The patent applies continuity of useful action by overlapping the pre-charge sequence with the voltage ramp-down process. Instead of completing pre-charge entirely before starting power off, the system initiates pre-charge and then transitions into controlled voltage reduction while pre-charge continues. This continuous approach maintains data retention benefits while minimizing the total time added to the power off process.
Solution Approach 2:
The pre-charge circuit is activated preliminarily upon detecting power off conditions, preparing memory banks before the main voltage reduction begins. This preliminary preparation is designed to be brief and efficient, securing critical data states without requiring the full duration that would significantly extend power off time.
4Reliability
If controlled ramp down sequence is used, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by using existing voltage sources within the memory device to perform the controlled ramp-down sequence. Rather than requiring entirely new external control circuitry, the system repurposes internal voltage sources and existing control logic to manage the power off sequence. This approach maintains data retention through controlled voltage reduction while minimizing increases in device complexity by leveraging available resources.
Solution Approach 2:
The second voltage source is designed with multi-functionality, serving both normal operation and the controlled ramp-down sequence during power off. This universal component performs multiple roles, reducing the need for dedicated specialized circuitry and thereby limiting the increase in device complexity while still enabling sophisticated voltage control for data retention.
Data Source
AI summary
A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes a sense amplifier and associated circuitry configured to detect a first threshold representative of a first external voltage ramping down during a power off of the memory device, and one or more switches triggered via the sense amplifier and associated circuitry to provide for a power off sequence for the memory bank based on using a second external voltage ramping down during the power off of the memory device.