Semiconductor Memory Power Rail Segmentation for Leakage Reduction
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing leakage current during standby modes, especially when switching between high and low frequency operations, which affects efficiency and reliability.
Innovation Solution
A semiconductor memory device with a power switching unit that efficiently switches between different power levels (VDD2H and VDD2L) to control power supply to various function blocks, optimizing power distribution during normal and standby modes by isolating power to specific global and local power rails based on operational frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is continuously supplied to all function blocks during standby mode, then operational readiness is maintained, but leakage current increases
Solution Approach 1:
The power supply system is segmented into multiple independent power rails (first global power rail, second global power rail, third global power rail, fourth global power rail) that can be selectively activated. During standby mode, only essential function blocks receive power through specific rails, while non-essential blocks are isolated, thereby reducing leakage current while maintaining operational readiness for critical functions.
Solution Approach 2:
The power supply configuration dynamically adapts based on operational mode. The power switching unit adjusts which power rails are active and how power is distributed to different function blocks depending on whether the device is in normal mode or standby mode, enabling optimal balance between reliability and energy loss at different operational states.
2Productivity
If high power VDD2H is supplied during high frequency operation, then performance is improved, but power consumption increases
Solution Approach 1:
The power supply voltage parameter is changed based on operational requirements. During high frequency operation, the power switching unit supplies high power VDD2H to enable maximum performance. During low frequency operation, it switches to low power VDD2L to reduce power consumption. This dynamic parameter adjustment allows the system to optimize the balance between productivity and energy usage according to actual operational demands.
Data Source
AI summary
A semiconductor memory device includes a first power supply unit configured to, in a normal mode of a high frequency operation, supply a first power from a first global power rail to a third global power rail and a fourth global power rail in a normal mode, and, in a standby mode of a high frequency option, supply the first power to the third global power rail and not supply the first power to the fourth global power rail, and, in a normal mode of a low frequency operation, supply a second power of a second global power rail to the third global power rail and the fourth global power rail, and, in a standby mode of a low frequency operation, supply the second power to the third global power rail and not supply the second power to the fourth global power rail.