Memory Controller Power Rails for Connected Standby Savings

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Solution Overview

Problem

High power consumption by memory devices in connected standby mode in mobile devices leads to reduced battery life, despite existing power management techniques failing to differentiate and adjust VDDQ and VDD2 voltage levels independently.

Innovation Solution

Implementing separate VDD2 and VDDQ power rails with a control signal to independently adjust VDDQ voltage during connected standby mode, allowing VDD2 voltage to remain unchanged, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory device operates in connected standby mode with unified power supply, then memory device can maintain operational state, but power consumption remains high

Engineering Contradiction:

Improvememory operational stateVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The power supply is segmented into two independent rails: VDD2 for the memory array and VDDQ for the input/output circuitry. This segmentation allows independent voltage control of each subsystem, enabling the memory array to maintain full voltage for data retention while the I/O circuitry operates at reduced voltage during connected standby mode, thereby reducing overall power consumption while maintaining operational reliability.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If existing power management techniques are used, then power supply is maintained for memory operation, but inability to differentiate VDDQ and VDD2 voltage levels results in unnecessary power consumption

Engineering Contradiction:

Improvevoltage control flexibilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The system implements dynamic voltage control by independently adjusting VDDQ voltage based on operational mode. During connected standby mode, VDDQ is reduced to a lower voltage level while VDD2 remains at full voltage. This dynamic adaptation allows the memory device to optimize power consumption according to actual operational requirements, achieving approximately 20mW savings during connected standby while maintaining full functionality when needed.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentEP4020130B1Power control of a memory device in connected standby state

Publication Date: 2026.03.04 INTEL CORP

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AI summary

Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.