Memory Array Power-Ready Signaling for Low-Inrush Startup
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Solution Overview
Problem
Existing memory arrays face significant inrush current issues during power-up due to simultaneous activation of large banks of SRAM cache and DRAM, which can tax power supply capabilities and introduce unnecessary delays in access times.
Innovation Solution
Implementing high-speed voltage monitoring circuits to rapidly determine when memory banks are powered on and ready for operation, using circuits with NMOS and PMOS transistors to generate power ready signals based on supply voltage and power down signals, reducing inrush current by staggering power-up times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If memory banks are powered on simultaneously, then power supply capability is taxed and inrush current increases, but access time is reduced
Solution Approach 1:
The patent uses voltage monitoring circuits to detect when the supply voltage reaches a threshold level before the memory banks are fully powered on. This preliminary detection allows the system to prepare for power-up sequencing in advance, enabling faster transition to operational state while controlling inrush current through staged activation of memory banks based on the monitored voltage levels.
2Power
If power up delays are introduced to manage inrush current, then inrush current is reduced, but memory access time increases
Solution Approach 1:
The patent implements dynamic power-up sequencing where the timing and staging of memory bank activation is adjusted based on real-time supply voltage monitoring. Instead of fixed delays, the system dynamically determines when to activate each memory bank based on whether the voltage threshold is reached, allowing the power-up sequence to adapt to actual power supply conditions and minimize both inrush current and access time.
Solution Approach 2:
The voltage monitoring circuits provide continuous feedback about the supply voltage status to the power management logic. This feedback mechanism allows the system to make informed decisions about when to activate memory banks, enabling precise control over the power-up sequence to optimize both inrush current management and access time performance based on actual voltage conditions.
Data Source
AI summary
A first memory instance comprises one or more first bitcell arrays and one or more peripheral circuits. The first memory instance further comprises a high-speed voltage monitoring circuit operable to monitor a supply voltage and a power down signal in the first memory instance, the high-speed voltage monitoring circuit further operable to provide an output power ready signal derived from the supply voltage and the power down signal such that the output power ready signal indicates when the power down signal is low and the supply voltage is high.