Memory Power Control for Volatile Data Remanence Protection
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Solution Overview
Problem
The data remanence property of volatile memory systems, which retains data after power off, creates security vulnerabilities that can be exploited by hackers through attacks like cold boot, allowing recovery of sensitive information.
Innovation Solution
A memory power control unit (MPCU) that includes a power controller and tamper detection circuit to reduce supply voltage to volatile memory upon detection of a tampering attempt, using timer circuits and logic circuits to control power output for a predetermined time, optionally accompanied by an increased reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the supply voltage to volatile memory is rapidly reduced to prevent data remanence, then security against cold boot attacks is improved, but potential false positives from legitimate reboots may occur
Solution Approach 1:
The tamper detection circuit monitors system state before a reboot occurs and prepares the power controller to distinguish between malicious and legitimate power interruptions. By detecting specific conditions (such as abnormal temperature or unauthorized power removal) before the voltage reduction is applied, the system can selectively activate protection only when needed, preventing false positives while maintaining security.
2Reliability
If complex tamper detection and power control circuits are implemented, then protection against data remanence attacks is improved, but device complexity and cost increase
Solution Approach 1:
The power controller is designed to serve multiple functions: it normally regulates supply voltage to the volatile memory during operation, and simultaneously provides rapid voltage reduction when tamper detection is triggered. This multi-functionality eliminates the need for separate protection circuitry, reducing overall device complexity while maintaining effective security protection.
Solution Approach 2:
The tamper detection circuit and power control functions are integrated into a unified security mechanism. The detection circuit directly interfaces with the power controller, which in turn connects to the volatile memory, creating a compact three-component system that combines monitoring, decision-making, and execution functions in a minimal configuration.
3Reliability
If the reduced supply voltage is applied for longer duration, then residual data is more completely discharged, but performance impact on legitimate operations increases
Solution Approach 1:
The power controller applies the reduced supply voltage in a controlled time period that is sufficient to discharge residual data from the volatile memory. By limiting the duration of voltage reduction to a specific window, the system achieves complete data clearance while minimizing impact on subsequent legitimate operations, as the memory can be quickly restored to normal voltage and functionality.
Data Source
AI summary
A memory power control unit, MPCU, is provided for preventing unauthorised access to data stored in a volatile memory, the MPCU comprising a power controller comprising an input configured to receive a signal from a tamper detection circuit, a first supply input configured 5 to receive a first supply voltage, a first reference input configured to receive a first reference voltage, a supply output configured to output a supply voltage to the volatile memory, a reference output configured to output a reference voltage to the volatile memory, wherein, in response to receipt of a signal at the input indicative of an attempt to tamper with the volatile memory, the power controller is configured to output a reduced supply voltage via the supply 10 output for a first predetermined time period, wherein the reduced supply voltage is less than the first supply voltage.