Memory Array Power Sequencing for Inrush Current Control
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Solution Overview
Problem
The significant inrush current during power-up of large memory arrays, such as SRAM cache and DRAM, poses a challenge to power supply capabilities in computing devices, particularly when components like processors and graphics processors are powered on simultaneously.
Innovation Solution
Implementing integrated delay elements, such as inverters and RC delay lines, to stagger the power-up sequence of memory instances and bitcell arrays within a memory array, reducing the inrush current by sequentially applying power to memory banks and bitcell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all memory instances and bitcell arrays are powered up simultaneously, then the memory array becomes operational faster, but the inrush current increases significantly
Solution Approach 1:
The memory array is divided into multiple memory instances, each containing bitcell arrays and peripheral circuitry. These instances are powered up independently through separate power control signals, allowing the system to segment the power-up process and control current draw from each instance separately rather than all at once.
Solution Approach 2:
The patent implements a delayed power-up sequence where power control signals are applied to memory instances at different times. The first memory instance receives the power signal immediately, while subsequent instances receive delayed power signals, creating a periodic or staggered activation pattern that spreads the inrush current over time.
2Power
If memory instances are powered up sequentially with delays, then inrush current is reduced, but the total power-up time increases
Solution Approach 1:
The patent applies partial action by powering up only one memory instance fully at a time while others remain in a lower power state. This allows the system to achieve adequate operational capacity with the first instance activated while managing current draw, rather than requiring all instances to be fully powered simultaneously for the system to function.
Solution Approach 2:
The patent changes the temporal parameter of power signal application by introducing controlled delays between instances. The delay parameter is optimized to balance current management requirements with performance requirements, allowing the system to adjust the power-up sequence characteristics to match operational needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively manages inrush current by delaying power signal propagation, reducing peak power consumption and alleviating strain on power supply components during device startup.
Implementation Method 1
providing a delayed bitcell array power ready signal at a first output terminal of the first memory instance
Implementation Method 2
integrated delay elements, such as inverters and RC delay lines
Data Source
AI summary
Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.