Memory Hierarchy Power Control for SoC Stall-Energy Balance
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Solution Overview
Problem
Existing systems-on-a-chip (SoC) with high-performance memory subsystems face inefficiencies due to imbalances in power management between compute agents and memory hierarchy, leading to increased energy expenditure without corresponding performance gains, particularly at higher memory hierarchy performance states.
Innovation Solution
A performance controller in the SoC-memory package monitors power ratios between memory and compute agents, adjusting memory and fabric performance states in a closed-loop manner to optimize energy efficiency by reducing memory stall cycles and balancing power usage across components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory hierarchy performance state is increased to reduce memory stall cycles, then compute agent performance is improved, but energy consumption increases
Solution Approach 1:
The patent implements dynamic performance state adjustment where the memory hierarchy performance state is continuously adapted based on real-time power ratio monitoring. The system transitions between different performance states (e.g., high-performance vs. low-power states) depending on the instantaneous balance between memory power consumption and compute agent power consumption, enabling dynamic optimization rather than static configuration
Solution Approach 2:
The system changes operational parameters by adjusting the memory hierarchy performance state based on the power ratio threshold comparisons. When the power ratio exceeds the threshold, the system transitions to a lower performance state with reduced energy consumption; when below the threshold, it transitions to a higher performance state with reduced memory stall cycles, thus optimizing the trade-off between performance and energy efficiency
2Productivity
If memory hierarchy performance state is increased to reduce memory stall cycles, then compute agent performance is improved, but overall power efficiency deteriorates
Solution Approach 1:
The system implements a closed-loop feedback mechanism where the power ratio (memory power divided by compute agent power) is continuously monitored and used to adjust memory hierarchy performance states. This feedback loop ensures that performance adjustments are driven by actual power consumption patterns, preventing energy waste while maintaining performance gains
Solution Approach 2:
The system dynamically changes the memory hierarchy performance state parameter based on real-time power ratio measurements. By comparing the current power ratio against predefined thresholds, the system adjusts performance parameters to optimize the balance between compute agent performance and overall power efficiency, reducing energy loss when high performance is not needed
3Use of energy by moving object
If memory power is reduced to improve power efficiency, then energy consumption is decreased, but memory stall cycles increase
Solution Approach 1:
The system dynamically adjusts memory performance states based on real-time power ratio monitoring. When power efficiency is prioritized and the power ratio indicates low compute demand, the system transitions to lower performance states with reduced memory power consumption. When performance becomes critical and the power ratio increases, the system dynamically switches to higher performance states to reduce memory stall cycles
Solution Approach 2:
The system changes the memory performance state parameter in response to power ratio threshold comparisons. By adjusting this parameter dynamically, the system can reduce memory power consumption when acceptable to do so, while increasing performance when memory stall cycles become problematic, thus optimizing the trade-off between energy efficiency and performance
4Loss of energy
If fabric performance state is adjusted to improve power efficiency, then energy consumption is optimized, but fabric power usage may increase or decrease
Solution Approach 1:
The system adjusts the fabric performance state parameter based on real-time power ratio measurements between memory and compute agent. When the power ratio indicates that memory power consumption is high relative to compute power, the system transitions to lower fabric performance states to reduce overall power efficiency losses. Conversely, when compute power is high, the system increases fabric performance to maintain data throughput
Solution Approach 2:
The fabric performance state is dynamically adjusted in response to changing power conditions. The system continuously monitors the power ratio and transitions between different fabric performance states (e.g., high-speed vs. low-power states) to optimize the balance between power efficiency and data transmission requirements, enabling adaptive power management
Data Source
AI summary
Some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. Some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (SoC)-memory package. The performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. When the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall SoC-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.