Semiconductor Memory Power Supply Protection Circuit
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Solution Overview
Problem
Semiconductor memory devices face issues with through current flow when power is turned on, particularly due to the RCTMOS circuit's design which can unintentionally short-circuit the power supply and ground during ESD stress, leading to unwanted current flow.
Innovation Solution
The semiconductor memory device incorporates a power supply protection circuit with transistors and resistors configured to manage the voltage between pads P1 and P2, using a trigger circuit with an RC timer to control the flow of current, ensuring the ON current only flows during surges and not when power is turned on, thereby reducing through current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the RCTMOS circuit is used for ESD protection, then ESD protection capability is improved, but unwanted through current flows when power is turned on
Solution Approach 1:
The patent applies preliminary action by using an RC trigger circuit to detect the rising edge of power voltage before the main power supply is fully activated. The circuit preemptively controls the ESD protection transistors to remain off during normal power-on, preventing through current flow before it can occur. Only when a genuine ESD surge is detected does the circuit activate the protection mechanism.
Solution Approach 2:
The patent introduces an RC trigger circuit as an intermediary between the power supply and the ESD protection circuit. This intermediary detects voltage transitions and selectively activates the ESD protection transistors only when needed, acting as a mediator that prevents direct through current flow while maintaining ESD protection capability. The trigger circuit distinguishes between normal power-on and ESD events.
2Reliability
If the ESD protection circuit allows current flow during surges, then protection effectiveness is improved, but current flow cannot be distinguished from normal power-on current
Solution Approach 1:
The patent applies parameter changes by utilizing the temporal characteristics of voltage transitions. The RC trigger circuit monitors the rate of change and timing of voltage transitions, distinguishing between the rapid transition of ESD surges and the gradual transition of normal power-on. This parameter-based differentiation simplifies the control logic while maintaining protection effectiveness.
Solution Approach 2:
The patent employs periodic action through the RC circuit's charging and discharging cycles. The RC trigger circuit naturally oscillates between states based on the timing characteristics of incoming voltage transitions. This periodic behavior creates distinct temporal patterns that differentiate ESD events from normal power-on, enabling simple threshold-based control without complex logic.
3Loss of energy
If transistors Tr9 and Tr11 are connected in series between pads P1 and P2, then through current is reduced, but circuit area increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the series connection of transistors Tr9 and Tr11 between pads P1 and P2. This arrangement is established before operation and remains in place throughout device lifecycle. The series connection is designed to have minimal area overhead while providing continuous through current blocking capability whenever the trigger circuit activates the protection state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents ON current flow when power is turned on, reducing unwanted current and protecting the interface circuit from damage, while allowing current to flow during surges, thus enhancing the device's operational reliability.
Implementation Method 1
a first RC circuit including a first resistor and a first capacitor connected in series between a second pad P2 and a second node GIN, and a second RC circuit including a second resistor and a second capacitor connected in series between the second pad P2 and the second node GIN
Implementation Method 2
a fourth transistor Tr14 having a first end electrically connected to the first pad P1, a second end electrically connected to the second pad P2, and a gate electrically connected to the second node GIN
Data Source
AI summary
A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.