Semiconductor Memory Power Switch Architecture
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Solution Overview
Problem
In semiconductor memory devices with multiple memory macros, the increasing circuit size leads to higher parasitic capacitance in internal power supply lines, resulting in large inrush currents and increased noise, which complicates power supply management and occupies more mounting area due to the need for multiple switches.
Innovation Solution
A semiconductor memory device design where the first power supply switches are located within memory macros to control power to memory cells, and a second power supply switch, external to the macros, controls power to memory peripheral circuits, reducing the current capacity and area required for the power supply switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple switches are provided for each memory peripheral circuit to control power supply, then power supply control is improved, but the mounting area increases
Solution Approach 1:
Multiple individual power supply switches for different memory peripheral circuits are merged into a single shared power supply switch. This switch controls power supply to all memory peripheral circuits simultaneously through a common power supply line, thereby reducing the total number of switches and the mounting area required while maintaining effective power supply control to all circuits.
2Adaptability or versatility
If circuit size is increased to accommodate multiple memory macros, then functionality is improved, but parasitic capacitance increases
Solution Approach 1:
Multiple memory peripheral circuits are connected through a common power supply line that shares a single power supply switch. This merging approach reduces the total number of power supply paths and switches in the system, thereby reducing the cumulative parasitic capacitance associated with multiple individual switches and their connecting pathways, while still providing power to all memory peripheral circuits.
3Ease of operation
If more switches are provided for power supply control, then power management is improved, but inrush current increases
Solution Approach 1:
Multiple individual power supply switches are merged into a single shared power supply switch that controls power to all memory peripheral circuits. This reduces the total number of switch turn-on events that could generate inrush currents. The single switch is designed with sufficient current capacity to handle the total current demand of all memory peripheral circuits, thereby managing inrush current more effectively than multiple smaller switches would individually.
Data Source
AI summary
A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.