Memory Power-Up Control Circuit Sequential Activation
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Solution Overview
Problem
Memory devices consume high current during power-up, potentially exceeding the maximum allowed current for electronic systems, leading to system shutdown.
Innovation Solution
A memory device with a power-up control circuit and boost voltage generators that activate internal circuits consecutively with delayed signals in response to power supply voltage and reset signals, dispersing current consumption over time to prevent excessive power draw.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory device activates all internal circuits simultaneously during power-up, then the memory device can be powered on quickly, but the current consumption exceeds the maximum allowed current causing system shutdown
Solution Approach 1:
The patent segments the internal circuits into multiple groups and activates them sequentially in stages rather than simultaneously. The power-up control circuit divides the activation process into multiple phases with delay times between successive activations, dispersing the current consumption over time to prevent exceeding the maximum allowed current while maintaining reasonable power-up speed.
2Power
If the memory device uses sequential activation of internal circuits with delay times, then the current consumption is dispersed over time, but the power-up process takes longer
Solution Approach 1:
The patent implements dynamic adjustment of activation timing based on system conditions. The power-up control circuit adjusts delay times between sequential activations adaptively, optimizing the balance between current consumption dispersion and power-up speed. The control mechanism dynamically manages the timing parameters to achieve the best performance under different operating conditions.
Data Source
AI summary
A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up. The first set of boost voltage generators may be configured to generate an internal boost voltage based on an external boost voltage and the first set of power-up signals. The first set of boost voltage generators may be configured to activate before the reset signal transitions from the first logic level to a second logic level opposite to the first logic level.