Memory Power Management via Wake Sleep Cycles

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Solution Overview

Problem

Computer memory power consumption is high due to the need for constant access capabilities, and existing low-power modes like self-refresh mode incur performance penalties when memory access patterns are unpredictable, making it inefficient to switch DIMMs in and out of low-power states.

Innovation Solution

Managing power to memory modules by maintaining a set of access requests and selectively powering up DIMMs from a low-power state to a high-power state only when needed, then returning them to low-power state after data transfer, allowing for predictable and efficient power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory is kept in high-power state for immediate access, then access speed is improved, but power consumption increases

Engineering Contradiction:
Improvememory access speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The memory system dynamically transitions between high-power and low-power states based on access patterns. The memory module operates in high-power state during active access periods and switches to low-power state during idle periods, optimizing the balance between speed and power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The memory system employs periodic wake/sleep cycles where the memory module alternates between active (high-power) and inactive (low-power) states. This periodic operation allows the system to achieve acceptable performance while significantly reducing average power consumption compared to continuous high-power operation.

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If memory switches to low-power mode, then power consumption is reduced, but access delay increases due to wake-up time

Engineering Contradiction:
Improvepower consumptionVSAvoidwake-up delay
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system performs preliminary actions by maintaining a queue of pending access requests and pre-waking the memory module when requests are detected. This allows the memory to be activated before actually needed, hiding the wake-up delay from the critical path and reducing perceived access latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory system maintains continuous useful action by keeping the memory module in high-power state during periods when access requests are pending or expected. This ensures that when accesses occur, the memory is already awake and ready, eliminating wake-up delays during active workloads.

Inventive Principle:
Principle #20Continuity of useful action

3Use of energy by moving object

If memory operates in self-refresh mode, then power consumption is reduced by 90%, but random access capability is lost

Engineering Contradiction:
Improvepower consumptionVSAvoidrandom access capability
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The memory system dynamically switches between self-refresh mode (losing random access) and normal operation mode (maintaining random access) based on the predictability and pattern of access requests. This allows the system to maximize power savings when random access is not needed while maintaining full functionality when it is required.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8068373B1Power management of memory via wake/sleep cycles
Publication Date: 2011.11.29 NETAPP INC
  • US8068373B1 patent drawing
  • US8068373B1 patent drawing
  • US8068373B1 patent drawing

AI summary

A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.