Semiconductor Memory Power Wiring via Intermediate Layer Routing
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Solution Overview
Problem
In NAND flash memory devices, the arrangement of cell source and well lines in the most upper layer complicates the routing of power supply wiring, leading to increased chip area, longer wiring lengths, reduced wiring width, and higher resistance, which can result in voltage drops and reduced operation speed.
Innovation Solution
The implementation of a semiconductor memory device with cell source and well lines arranged in curved or meshed patterns in the second metal wiring layer, allowing power supply lines to be routed efficiently between page buffers, reducing resistance and enabling simultaneous operation of circuits while maintaining a compact chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell source lines and cell well lines are arranged in the most upper layer, then the memory cell array can be densely integrated, but the power supply wiring routing becomes complicated and chip area increases
Solution Approach 1:
The patent introduces a third wiring layer (intermediate layer) between the bit line layer and the cell source/well line layer. This dimensional addition allows power supply wiring to route through the intermediate layer without conflicting with the most upper layer's memory cell structures, thus maintaining high cell density while providing adequate power supply routing paths without increasing chip area.
2Reliability
If power supply wiring is routed through the row decoder area, then power can be supplied to distant circuits, but the wiring length increases and wiring resistance increases
Solution Approach 1:
The patent segments the power supply wiring into multiple paths by utilizing both the intermediate wiring layer and the most upper wiring layer. Power can be distributed through different layers to reach various circuits, reducing the length of individual wiring segments and thereby reducing overall wiring resistance while maintaining reliable power supply to distant circuits.
3Area of stationary object
If the wiring width is reduced to fit the chip area, then the chip area is minimized, but the wiring resistance increases and voltage drop occurs
Solution Approach 1:
By adding the intermediate wiring layer, the patent provides an additional dimensional space for power supply wiring. This allows wider wiring paths to be created in the intermediate layer without occupying additional chip area, as the extra width is achieved through the third layer rather than expanding the planar footprint. Consequently, wiring resistance is reduced and voltage drop is minimized while maintaining compact chip dimensions.
Data Source
AI summary
A memory cell array in a semiconductor substrate has a plurality of memory cells arranged in rows and columns. A first circuit is located at one end of the memory cell array in a column direction. A second circuit is located at the other end of the memory cell array in the column direction. A first wire is located above the memory cell array between the first circuit and the second circuit. The first wire is located in a most upper layer in the semiconductor substrate to supply power to the second circuit.