Multi-Die Memory Power Management via Wrap-Around Counter
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Solution Overview
Problem
Power management in memory devices becomes challenging when multiple memory devices operate concurrently, leading to potential exceeding of power consumption specifications and availability issues, as existing techniques often rely on external controllers to stagger high-power operations.
Innovation Solution
Implementing a wrap-around counter mechanism within multi-die packages to manage power by allowing each die to participate in a sequence of operations, sharing a clock signal to pause and resume operations based on high-current demand periods, thereby mitigating concurrent high-current demand periods without external controller intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory devices operate concurrently, then productivity is improved, but power consumption exceeds specifications
Solution Approach 1:
The patent implements a wrap-around counter mechanism that periodically assigns time slots to different dies in a multi-die package. Each die is granted access to high-current demand operations only during its assigned time slot, creating a periodic scheduling system that distributes power consumption over time while maintaining overall system productivity through concurrent operation capability.
2Power
If external controllers are used to stagger high-power operations, then power consumption is controlled, but device complexity increases
Solution Approach 1:
The patent enables each die within the multi-die package to autonomously monitor the wrap-around counter and determine when its assigned time slot occurs. Each die independently controls its own high-current demand operations without requiring external controller intervention, thereby reducing system complexity while maintaining power consumption control through self-service time-slot-based scheduling.
Data Source
AI summary
Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.