Memory Die PPM Connectivity Check for Reliable Peak Power Control

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Solution Overview

Problem

Existing peak power management (PPM) systems in memory sub-systems cannot be effectively validated for connectivity and operation after assembly, leading to potential failures and decreased performance.

Innovation Solution

A connectivity check is performed using existing signal connections to verify proper physical connectivity and operation of PPM components within memory devices, involving a test sequence where test values are propagated and compared to expected values to detect any connectivity faults.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If PPM systems are implemented in memory sub-systems without connectivity validation, then power management functionality is provided, but reliability deteriorates due to potential undetected failures

Engineering Contradiction:
ImprovePPM system reliabilityVSAvoidvalidation system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The PPM component performs self-validation by using its own signal connections to check connectivity and operation. The system validates itself without requiring external validation equipment or complex system-level controllers, thus improving reliability while avoiding additional complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent uses existing signal connections as intermediaries to perform the validation. These connections serve dual purposes: normal PPM operation and connectivity validation, eliminating the need for separate validation pathways and maintaining simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Difficulty of detecting and measuring

If system-level controllers are used to validate PPM connectivity, then detection accuracy improves, but device complexity increases

Engineering Contradiction:
Improveconnectivity fault detectionVSAvoidvalidation system complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The PPM component autonomously performs connectivity validation using its own signal connections and test value propagation mechanisms. This self-service approach achieves effective fault detection without requiring external system-level controllers, thereby maintaining system simplicity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The existing signal connections are designed to serve multiple functions: normal PPM signal transmission and connectivity validation. This multi-functionality allows the system to achieve detection capability without adding dedicated validation hardware or increasing overall complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If comprehensive PPM validation is implemented, then reliability improves, but processing time increases

Engineering Contradiction:
ImprovePPM system validationVSAvoidvalidation processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The connectivity validation is performed periodically or on-demand rather than continuously. The PPM component can execute validation sequences at appropriate intervals or when triggered by specific conditions, achieving reliable detection while minimizing time loss through non-intrusive periodic checking.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The validation process uses rapid test value propagation and comparison techniques that quickly traverse the signal connections. By rushing through the validation sequence efficiently using existing fast signal paths, the system achieves comprehensive checking with minimal time penalty.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS12548634B2Peak power management connectivity check in a memory device
Publication Date: 2026.02.10 MICRON TECHNOLOGY INC
  • US12548634B2 patent drawing
  • US12548634B2 patent drawing
  • US12548634B2 patent drawing

AI summary

A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.