Memory PPR Control Using Read Comparison for Intermittent Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in detecting intermittent errors during post package repair (PPR) operations due to the increasing complexity of manufacturing processes, making it difficult to identify and correct sporadic defects.
Innovation Solution
A memory system and control circuit that includes a PPR control circuit to compare data values before and after PPR operations, determining the success or failure of the repair by comparing data values in anti-fuse arrays, and allowing for both hard and soft repair methods to manage defective memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PPR operation is performed on memory devices with increased integration degree, then manufacturing capability is improved, but detection of intermittent errors becomes more difficult
Solution Approach 1:
The patent applies preliminary action by performing a read operation on the memory cell array before the PPR operation to obtain a first read data, and then performing another read operation after the PPR operation to obtain a second read data. This preliminary data capture enables comparison to detect intermittent errors that occur during the PPR process, resolving the detection difficulty while maintaining manufacturing capability.
2Reliability
If PPR operation is performed to replace defective memory cells, then reliability is improved, but programming time increases
Solution Approach 1:
The patent implements feedback by comparing the first read data obtained before PPR operation with the second read data obtained after PPR operation. Based on this comparison feedback, the system determines whether the PPR operation was successful or if an intermittent error occurred. This feedback mechanism enables rapid error detection and appropriate response, reducing the overall time loss by avoiding lengthy reprogramming cycles and ensuring reliable repair outcomes.
Data Source
AI summary
A memory system including a memory device that receives a plurality of signals including a post package repair (PPR) command from a host, wherein the memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, and anti-fuse memory cells, and a PPR control circuit that transmits to the host whether a PPR operation on a defective memory cell of the memory cell array has passed.