Memory PRBS Testing for Read and Write Error Isolation

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Solution Overview

Problem

Existing memory device testing methods struggle to distinguish between read and write errors accurately, leading to difficulties in identifying the source of input and output errors.

Innovation Solution

A memory system and method utilizing shared seed values to generate pseudo-random binary sequences (PRBS) in both the memory controller and device, enabling independent evaluation of these sequences to determine the source of errors in read and write processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional input and output testing is performed on memory devices, then the testing process can be completed, but it is difficult to clearly distinguish whether errors are generated in the read process or write process

Engineering Contradiction:
Improveerror source identification accuracyVSAvoidtest system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces PRBS generators and evaluators as intermediary components that generate and compare pseudo-random binary sequences at both the memory controller and memory device. These intermediaries enable precise error source identification by comparing transmitted and received PRBS sequences, allowing differentiation between read and write errors without significantly increasing overall system complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the testing parameter from simple data transmission to using pseudo-random binary sequences with specific properties. By using PRBS with defined lengths and patterns, the system can more effectively identify error sources while maintaining manageable test complexity through standardized sequence generation.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If comprehensive input and output testing is performed to improve reliability, then error detection capability is enhanced, but test time increases

Engineering Contradiction:
Improveinput and output test reliabilityVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by generating PRBS sequences before the actual memory test operations. The PRBS generators are pre-configured with specific sequences, and the evaluators are prepared to compare results, enabling faster and more reliable testing without extending the overall test time significantly.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuity of useful action by having PRBS sequences continuously generated and compared throughout the testing process. Rather than performing separate discrete tests, the system continuously monitors data integrity using PRBS, improving reliability without adding significant time overhead.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250364070A1Memory system and method for testing memory system
Publication Date: 2025.11.27 SAMSUNG ELECTRONICS CO LTD
  • US20250364070A1 patent drawing
  • US20250364070A1 patent drawing
  • US20250364070A1 patent drawing

AI summary

Provided is a memory system, including a memory controller including a seed generator configured to generate a seed value, and a first pseudo-random binary sequence (PRBS) generator configured to generate a first PRBS based on the seed value, and a memory device including a second PRBS generator configured to receive the seed value from the memory controller and generate a second PRBS based on the seed value, an evaluator system including at least one of a first evaluator configured to evaluate the first and second PRBSs, the first evaluator being included in the memory controller, or a second evaluator configured to evaluate the first and second PRBSs, the second evaluator being included in the memory device, and the memory controller may be further configured to perform a read test using the first evaluator, or the memory device may be further configured to perform a write test using the second evaluator.