Memory Access Pre-Arbitration for Multi-Core Cache Coherency
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Solution Overview
Problem
Multi-core systems face challenges with coherency issues due to multiple processing cores accessing the same memory address, leading to operational inefficiencies and outdated data retrieval, particularly when software cache maintenance operations are slow and resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank, along with an arbiter circuit, ensures coherent data access by determining priority and credit thresholds for memory access requests, and maintains coherency using hardware-based solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive resource consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency management system. The snoop filter bank and arbiter circuit are implemented in hardware within the memory controller, automatically detecting and resolving coherency conflicts through dedicated hardware logic rather than software execution, thereby eliminating the performance overhead of software while maintaining coherency reliability
Solution Approach 2:
The snoop filter bank acts as an intermediary component between the cache and memory subsystems. It intercepts and filters memory access requests, identifying coherency conflicts before they propagate through the system. This intermediary hardware structure enables automatic coherency management without requiring software intervention, resolving the contradiction between reliable coherency maintenance and operational efficiency
2Productivity
If hardware-based coherency management is implemented, then operational efficiency improves, but device complexity increases due to additional components
Solution Approach 1:
The patent merges the snoop filter bank, cache tag bank, and arbiter circuit into a single integrated memory controller unit. By combining these previously separate hardware components into one unified structure, the patent reduces overall system complexity while maintaining the operational efficiency benefits of hardware-based coherency management. The integrated design allows components to share resources and coordinate automatically
Solution Approach 2:
The memory controller is designed with multi-functional capabilities, handling both memory management and coherency enforcement within a single device. The arbiter circuit serves multiple purposes by managing both data path arbitration and coherency conflict resolution. This universal approach allows the hardware to perform multiple functions without proportionally increasing complexity, as components are designed to handle diverse operations
3Productivity
If multiple processing cores access shared memory simultaneously, then processing throughput increases, but coherency issues worsen leading to outdated data retrieval
Solution Approach 1:
The snoop filter bank performs preliminary filtering of memory access requests before they reach the cache or memory. By pre-processing requests and identifying potential coherency conflicts in advance, the system can resolve issues before outdated data is retrieved. This preliminary hardware-based action enables multiple cores to access shared memory simultaneously while maintaining data coherency through proactive conflict detection and resolution
Data Source
AI summary
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.