Semiconductor Memory Pre-Discharge Timing Control
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Solution Overview
Problem
Phase-change memory apparatuses face read/write failures due to the time required for bit line discharge operations, which can exceed standard operation times, leading to inefficiencies and potential failures.
Innovation Solution
A semiconductor memory apparatus with a bit line discharge block and a discharge controller that performs a pre-discharge operation before enabling the active mode signal, allowing for a predetermined amount of discharge before regular discharge, thereby reducing the overall discharge time and minimizing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit line discharge operation is performed before read/write operation, then the bit line is sufficiently discharged, but the operation time exceeds the required standard time
Solution Approach 1:
The patent applies preliminary action by performing a pre-discharge operation before the active mode signal is enabled. The discharge controller generates a bit line discharge signal in advance to discharge the bit line partially before the main discharge operation, ensuring sufficient discharge without extending the critical read/write operation time.
Solution Approach 2:
The discharge operation is segmented into two phases: a pre-discharge phase that occurs before the active mode signal is enabled, and a main discharge phase that occurs during the active mode. This segmentation allows the discharge to be completed in stages, ensuring reliability while meeting timing requirements.
2Productivity
If the bit line discharge time is reduced to meet operation time standards, then the operation time is within requirements, but the discharge may be insufficient leading to read/write failures
Solution Approach 1:
The pre-discharge operation is performed in advance before the active mode signal is enabled, preparing the bit line for the subsequent read/write operation. This preliminary action ensures that the bit line is sufficiently discharged without requiring extended discharge time during the critical operation window.
Solution Approach 2:
The discharge controller dynamically controls the discharge timing by generating the bit line discharge signal based on the timing of the active mode signal. The pre-discharge occurs at an optimal time before the active mode, adapting the discharge schedule to meet both speed and reliability requirements.
3Loss of time
If a pre-discharge operation is implemented, then the actual discharge time during active mode is reduced, but the control complexity increases
Solution Approach 1:
The discharge controller performs multiple functions: it generates the bit line discharge signal for pre-discharge, controls the timing relative to the active mode signal, and ensures sufficient discharge before read/write operations. This multi-functionality is achieved through a single integrated controller rather than separate circuits for each function.
Solution Approach 2:
The discharge controller acts as an intermediary between the active mode signal and the bit line discharge block. It receives the active mode signal timing information and generates the appropriately timed bit line discharge signal, mediating the coordination between different parts of the system without requiring complex interconnections.
Data Source
AI summary
A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated, and a bit line discharge block coupled to the bit line and configured to discharge the bit line in response to the bit line discharge signal.