Memory Pre-Drivers with Adjustable Transition Rates
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Solution Overview
Problem
High-speed operation of memory devices is hindered by signal reflection and voltage swing issues on data buses, which can lead to glitches and erroneous data input due to conflicting requirements for transition rates and slew rates during on-die termination (ODT) operations.
Innovation Solution
The memory device employs a configuration with pre-drivers and drivers that adjust their current drivabilities and transition rates during ODT and data output operations, using transistors and resistance elements to manage signal termination and reduce voltage swing, ensuring proper impedance matching and minimizing glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bus termination is applied to prevent signal reflection, then signal quality is improved, but voltage swing increases and transition rate decreases
Solution Approach 1:
The patent applies dynamics by making the pre-driver's current drivability adjustable based on operation mode. During ODT operation, the pre-driver switches to a lower current drivability mode that produces slower transition rates, while during data output it uses higher current drivability for faster transitions. This dynamic adaptation resolves the contradiction between signal quality (requiring slow transitions for proper termination) and speed (requiring fast transitions for high-performance operation).
Solution Approach 2:
The patent changes the electrical parameters of the pre-driver by switching between different current drivability states. The pre-driver circuit is designed to operate with different effective resistance values or current capabilities depending on the selected mode (ODT vs. data output). This parameter change allows the system to optimize transition rates for each specific operation type, resolving the trade-off between signal integrity and switching speed.
2Speed
If high current drivability is used for fast data output, then speed is improved, but signal reflection and glitches increase
Solution Approach 1:
The system dynamically adjusts the pre-driver's current drivability based on the operation mode. During data output operations, the pre-driver operates in high current drivability mode to enable fast transitions and high-speed data transmission. During ODT operations, it switches to low current drivability mode to prevent signal reflection and glitches. This dynamic switching resolves the contradiction between speed and signal reflection.
Solution Approach 2:
The patent implements preliminary action by selecting the appropriate pre-driver current drivability mode before the actual data output or ODT operation begins. The mode selection is controlled by a control signal that prepares the pre-driver in advance for the upcoming operation type, ensuring that the correct transition rate is applied from the start of each operation, thereby preventing signal reflection before it can occur.
3Reliability
If low transition rate is used during ODT, then signal reflection is reduced, but data output speed decreases
Solution Approach 1:
The pre-driver's current drivability is dynamically changed based on operation mode. During ODT operations, the system uses low transition rates to prevent signal reflection and ensure reliable termination. During data output operations, it switches to high transition rates to maximize data throughput. This dynamic adaptation resolves the contradiction between signal reflection prevention and data output productivity.
Solution Approach 2:
The patent changes the transition rate parameter of the pre-driver according to the operation mode. By switching between different transition rate settings (fast for data output, slow for ODT), the system optimizes both signal integrity during termination and data transmission speed during output operations, thereby resolving the productivity-reliability trade-off.
Data Source
AI summary
According to one embodiment, during a transition to and from a state assumed while a signal is being received from outside a memory device at the terminal, a first pre-driver outputs a first signal which transitions at a lower rate than that during a transition to and from a state assumed while a signal is being output to outside the memory device at the terminal. During a transition to and from a state assumed while a signal is being received from outside the memory device at the terminal, a second pre-driver outputs a second signal which transitions at a lower rate than that during a transition to and from a state assumed while a signal is being output to outside the memory device at the terminal.