Non-volatile Memory Page Buffer Precharge Circuit for String Select Transistor Programming
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Solution Overview
Problem
Non-volatile memory devices face challenges in narrowing the distribution of threshold voltage for string select transistors, which limits their operation margin, as they cannot be inhibited via channel boosting and require high bit-line voltages during programming.
Innovation Solution
A non-volatile memory device with a control logic circuit generating program and erase signals, and a voltage generator producing corresponding voltages, along with precharge and discharge circuits to manage bit-line voltages, enabling efficient programming and erasing of string select transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to the bit-line to program the string select transistor, then the programming operation is effective, but the device complexity increases due to the need for additional voltage generation and control circuits
Solution Approach 1:
The precharge transistor is integrated into the existing page buffer circuit, allowing the page buffer to serve dual functions: traditional read operations and string select transistor programming. This eliminates the need for separate voltage generation and control circuits, reducing device complexity while maintaining programming effectiveness through the same bit-line voltage application mechanism
Solution Approach 2:
The page buffer circuit generates and applies the necessary high voltage to the bit-line itself during programming operations, without requiring external voltage generation circuits. The precharge transistor within the page buffer automatically controls the voltage application, making the circuit self-sufficient and reducing overall system complexity
2Device complexity
If the string select transistor is inhibited only with bit-line voltage, then the device structure is simpler, but the operation margin is reduced compared to channel boosting methods
Solution Approach 1:
The invention changes the voltage parameter applied to the bit-line from standard operating voltages to elevated high voltages during programming operations. This parameter change compensates for the simpler inhibition mechanism, providing sufficient operation margin by ensuring the string select transistor can be reliably programmed and distinguished from inhibited transistors without requiring complex channel boosting structures
Data Source
AI summary
In some embodiments, a non-volatile memory device includes a control logic circuit configured to generate a program signal and an erase signal based on control signals, a voltage generator configured to generate a program voltage and an erase voltage based on the program signal and the erase signal, a memory cell array including a memory cell, a string select transistor coupled to the memory cell, a bit-line coupled to the string select transistor, and a string select line coupled to the string select transistor, and a page buffer circuit coupled to the bit-line, and including a first precharge transistor that is configured to operate based on the program signal and the erase signal. The first precharge transistor is configured to apply the program voltage and the erase voltage to the bit-line in response to the program signal and the erase signal, respectively.