Memory Device Precharge Circuit Segmentation for RC Delay Reduction
Solution Overview
Problem
Current memory devices face challenges in reducing the pre-charge time of global bit lines, which affects the overall performance by increasing the row address to column address delay and data reading time due to high resistance-capacitance (RC) delay.
Innovation Solution
The implementation of a pre-charge method that includes a first pre-charge circuit between sub-arrays within the memory cell array and a second pre-charge circuit outside the array, which pre-charges the global bit lines with different voltages, reducing RC delay and pre-charge time by using clamped currents from external power supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single pre-charge circuit is used outside the memory cell array, then the circuit structure is simple, but the pre-charge time of global bit lines is long due to high RC delay
Solution Approach 1:
The pre-charge circuit is divided into two segments: a first pre-charge circuit located inside the memory cell array between sub-arrays, and a second pre-charge circuit located outside the memory cell array. This segmentation allows the first circuit to quickly reduce RC delay for local bit lines while the second circuit provides overall pre-charge control, thereby reducing total pre-charge time without requiring a completely complex new structure.
Solution Approach 2:
The first pre-charge circuit performs preliminary pre-charging of the global bit lines before the second pre-charge circuit completes the pre-charge process. By arranging the first pre-charge circuit inside the memory cell array, it can earlier and more effectively reduce the RC delay, preparing the bit lines for faster subsequent operations.
2Speed
If pre-charge circuits are arranged inside the memory cell array between sub-arrays, then the RC delay is reduced and pre-charge speed is improved, but the device structure becomes more complex
Solution Approach 1:
The first pre-charge circuit is specifically positioned at locations where RC delay has the greatest impact on performance - between sub-arrays within the memory cell array. This local placement optimizes pre-charge speed for the most critical regions without unnecessarily complicating the entire device structure. The circuit is strategically located to maximize its effectiveness in reducing RC delay where it matters most.
Data Source
AI summary
A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first pre-charge circuit located between a plurality of sub arrays included in a memory cell array and pre-charging the first global bit line with a second pre-charge voltage by using a second pre-charge circuit located outside the memory cell array.