Memory Precharge Circuitry to Reduce Bit Line Power
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Solution Overview
Problem
Static random access memories (SRAMs) and content-addressable memories (CAMs) face significant power consumption issues due to high dynamic power in bit line precharge operations, with existing solutions like voltage scaling causing speed and stability problems.
Innovation Solution
A precharge circuitry that limits bit line precharge levels to 10-80% or 20-80% lower than the supply voltage during a single precharge cycle, using PMOS or NMOS transistors to set bit line precharge levels without substantial delay, thereby reducing dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage scaling is used to reduce bit line precharge power consumption, then power consumption is reduced, but speed and stability deteriorate
Solution Approach 1:
The patent changes the voltage parameter by introducing a limited precharge voltage level (VPRE) that is lower than the full supply voltage (VDD) but higher than ground. This intermediate voltage level reduces the voltage swing on bit lines during precharge operations, thereby reducing dynamic power consumption (P ∝ CV²f) while maintaining sufficient voltage margin for stable memory operation and acceptable speed performance.
2Use of energy by moving object
If voltage scaling is used to reduce bit line precharge power consumption, then power consumption is reduced, but speed deteriorates
Solution Approach 1:
The patent modifies the voltage parameter by using an intermediate precharge voltage level (VPRE) between ground and full supply voltage (VDD). This reduces the voltage swing magnitude during precharge, lowering dynamic power consumption while maintaining adequate charging speed through proper transistor sizing and circuit design that ensures the precharge operation completes within the required time margin.
3Reliability
If full supply voltage is applied to bit lines during precharge, then stability is maintained, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameter from full supply voltage (VDD) to a limited precharge voltage level (VPRE) that is lower than VDD but higher than ground. This intermediate voltage level provides sufficient noise margin and stability for memory operation while reducing the dynamic power consumption of bit line precharge, since power is proportional to the square of the voltage swing (P ∝ CV²f).
Solution Approach 2:
The patent applies partial precharge action by charging bit lines only to the necessary voltage level (VPRE) rather than fully to supply voltage (VDD). This partial charging action is sufficient to establish stable logic levels and provide adequate noise margins, while avoiding the excessive power consumption that would result from charging to full supply voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces dynamic power consumption in SRAMs and CAMs while maintaining memory stability and performance, offering power-efficient operation without impacting speed or stability.
Implementation Method 1
using PMOS or NMOS transistors to set bit line precharge levels without substantial delay
Data Source
AI summary
The present disclosure relates to a precharge circuitry for bit lines of an array of memory cells, the precharge circuitry comprising a precharge and limiting unit configured to precharge a first bit line and a second bit line, the precharge and limiting unit further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of a read and/or write operation of any of the memory cells, wherein the precharge and limiting unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay. The disclosure further relates to a memory comprising a plurality of memory cells arranged in columns and rows, and at least one precharge circuit, wherein the precharge circuit is connected to a first bit line and a second bit line of all memory cells within a column, wherein each precharge circuit is configured to limit the first bit line to a first bit line precharge level and the second bit line to a second bit line precharge level during a precharge cycle.