Memory Pre-charge Circuits for Dynamic Bit Line Usage
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Solution Overview
Problem
The pre-charging and detection of data values in memory arrays lead to significant power consumption in computing systems, particularly in mobile devices, as data lines are repeatedly charged and read, necessitating a method to reduce this power consumption.
Innovation Solution
The implementation of a memory system with pre-charge circuits that maintain data on data lines between read operations, allowing for selective output of subsets of data based on page addresses, thereby minimizing the need for repeated pre-charging and reducing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data lines are pre-charged to a known logic level before each read operation, then reliable data detection is achieved, but power consumption increases due to repeated charging
Solution Approach 1:
The patent applies preliminary action by pre-charging data lines only when necessary (detected through address comparison) rather than before every read operation. The system determines in advance whether pre-charging is needed by comparing the current page address with the previously accessed page address, thereby performing the pre-charging action only when it will be useful for the upcoming read operation.
Solution Approach 2:
The patent implements periodic action by replacing continuous pre-charging before every read operation with selective periodic pre-charging. The pre-charge operation is performed periodically only when the address comparison logic determines that the current read operation targets a different page than the previous operation, thereby reducing the frequency of pre-charging events while maintaining data detection reliability.
2Measurement precision
If data lines are pre-charged before every read operation, then data detection accuracy is maintained, but read operation speed decreases due to repeated pre-charging cycles
Solution Approach 1:
The system performs preliminary address comparison before deciding whether to pre-charge data lines. By evaluating the address match condition in advance, the system avoids unnecessary pre-charging operations that would delay subsequent read operations, thereby maintaining data detection accuracy while improving read operation speed through selective pre-charging.
Solution Approach 2:
The patent replaces continuous pre-charging with periodic selective pre-charging based on address comparison results. This periodic approach maintains data detection accuracy by pre-charging only when needed (periodically rather than continuously), thereby improving overall read operation speed by eliminating redundant pre-charging cycles.
3Ease of operation
If all data lines are pre-charged to a known logic level, then complete data readiness is achieved, but power consumption increases due to charging unused lines
Solution Approach 1:
The patent applies local quality by differentiating the treatment of data lines based on their relevance to the current read operation. Instead of uniformly pre-charging all data lines, the system selectively pre-charges only those lines corresponding to the specific page being accessed, as determined by address comparison. This localized approach ensures data readiness for required lines while avoiding energy waste on unused lines.
Solution Approach 2:
The system performs preliminary address comparison to identify which specific data lines will be needed for the upcoming read operation. Based on this preliminary determination, only the relevant data lines are pre-charged, thereby achieving complete data readiness for the required lines while minimizing energy waste by excluding unnecessary pre-charging of unrelated lines.
Data Source
AI summary
An apparatus, system, and method are contemplated in which the apparatus may include a memory with a plurality of pages, circuitry, and a plurality of pre-charge circuits. The circuitry may be configured to receive a first read command and address, corresponding to a given page. The plurality of pre-charge circuits may be configured to charge a plurality of data lines to a predetermined voltage. The circuitry may be configured to read data values from the memory, and transfer the data values to the plurality of data lines. The plurality of pre-charge circuits may be configured to maintain the data on the plurality of data lines. The circuitry may select a first subset of the maintained data, receive a second read command and a second address by the memory, and select a second subset of the maintained data responsive to a determination that the second address corresponds to the given page.